all_01.tan.summary

eda 开发数字钟的设计具体编程代码和开发流程与设计图

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.997 ns
From           : KEY[6]
To             : clock_spk:17|count[10]
From Clock     : --
To Clock       : CLK20M
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 23.646 ns
From           : clock2:inst2|clkout
To             : WORKING_LED
From Clock     : CLK20M
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.573 ns
From           : KEY[2]
To             : clock_spk:17|clkout
From Clock     : --
To Clock       : CLK20M
Failed Paths   : 0

Type           : Clock Setup: 'CYC_PLL:inst|altpll:altpll_component|_clk0'
Slack          : 5.841 ns
Required Time  : 24.00 MHz ( period = 41.666 ns )
Actual Time    : 33.35 MHz ( period = 29.984 ns )
From           : hhmmss:inst8|ss[2]
To             : debugled:10|temp_seg[0]
From Clock     : CYC_PLL:inst|altpll:altpll_component|_clk0
To Clock       : CYC_PLL:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'CYC_PLL:inst|altpll:altpll_component|_clk1'
Slack          : 6.330 ns
Required Time  : 60.00 MHz ( period = 16.666 ns )
Actual Time    : 96.75 MHz ( period = 10.336 ns )
From           : clock_spk:17|count[6]
To             : clock_spk:17|clkout
From Clock     : CYC_PLL:inst|altpll:altpll_component|_clk1
To Clock       : CYC_PLL:inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'KEY[11]'
Slack          : N/A
Required Time  : None
Actual Time    : 202.39 MHz ( period = 4.941 ns )
From           : hhmmss:inst8|si_mm[2]
To             : hhmmss:inst8|si_mm[2]
From Clock     : KEY[11]
To Clock       : KEY[11]
Failed Paths   : 0

Type           : Clock Setup: 'KEY[10]'
Slack          : N/A
Required Time  : None
Actual Time    : 214.22 MHz ( period = 4.668 ns )
From           : hhmmss:inst8|si_ss[4]
To             : hhmmss:inst8|si_ss[4]
From Clock     : KEY[10]
To Clock       : KEY[10]
Failed Paths   : 0

Type           : Clock Setup: 'KEY[12]'
Slack          : N/A
Required Time  : None
Actual Time    : 229.78 MHz ( period = 4.352 ns )
From           : hhmmss:inst8|si_hh[5]
To             : hhmmss:inst8|si_hh[7]
From Clock     : KEY[12]
To Clock       : KEY[12]
Failed Paths   : 0

Type           : Clock Hold: 'CYC_PLL:inst|altpll:altpll_component|_clk1'
Slack          : 0.822 ns
Required Time  : 60.00 MHz ( period = 16.666 ns )
Actual Time    : N/A
From           : clock40:inst3|count[5]
To             : clock40:inst3|count[5]
From Clock     : CYC_PLL:inst|altpll:altpll_component|_clk1
To Clock       : CYC_PLL:inst|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'CYC_PLL:inst|altpll:altpll_component|_clk0'
Slack          : 1.031 ns
Required Time  : 24.00 MHz ( period = 41.666 ns )
Actual Time    : N/A
From           : clockall:9|14
To             : clockall:9|14
From Clock     : CYC_PLL:inst|altpll:altpll_component|_clk0
To Clock       : CYC_PLL:inst|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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