db1200.cfg

AMD AU1200 BDSL配置文件.AU1200开发仿真器所用配置参数.

;rev 1.0

; bdiGDB configuration file for Alchemy DBAu1200 board
; ----------------------------------------------------

[INIT]
; Setup CPU PLL to 396 MHz
WM32	0xB1900060	0x00000021	; sys_cpupll	;CPU_PLL Configuration

; Setup AUX PLL to 96 MHz for LCD
WM32	0xB1900064	0x00000008	; sys_auxpll	;AUX_PLL Configuration

; Setup Endianess
;  sys_endian
WM32	0xB1900038  0x00000001  ; sys_endian	;Set to Little Endian
WCP0    16          0x00000003	; cp0_config	;Set KSEG0 CCA = 3

; Setup Static Bus Controller

;	RCS0:  2x32MB Spansion S29GL256N10T MirrorBit Flash - 100ns, Vio=3V
WM32	0xB4001000	0x002D0043	; mem_stcfg0	;RCS0 Configuration
WM32	0xB4001004	0x066181D7	; mem_sttime0	;RCS0 Timing
WM32	0xB4001008	0x11C03F00	; mem_staddr0	;RCS0 Address

;	RCS1: NAND
;WM32	0xB4001010	0x00420045	; mem_stcfg1	;RCS1 Configuration
;WM32	0xB4001014	0x00007774	; mem_sttime1	;RCS1 Timing
;WM32	0xB4001018	0x12000FFF	; mem_staddr1	;RCS1 Address

;	RCS2: CPLD Board Logic, LAN91C111, IDE PIOmode4
;WM32	0xB4001020	0x862D00C6	; mem_stcfg2	;RCS2 Configuration
;WM32	0xB4001024	0x14434C12	; mem_sttime2	;RCS2 Timing
;WM32	0xB4001028	0x11803F00	; mem_staddr2	;RCS2 Address

;	RCS3: PCMCIA 250ns
;WM32	0xB4001030	0x00040042	; mem_stcfg3	;RCS3 Configuration
;WM32	0xB4001034	0x280E3E07	; mem_sttime3	;RCS3 Timing
;WM32	0xB4001038	0x10000000	; mem_staddr3	;RCS3 Address

; Setup DDR SDRAM Controller
;	 DCS[0]:  128MB DDR2-533 Samsung K4T51163QB-GCD5 (8Mbit x 16 x 4bank x 2devices)
;	 DCS[1]:  128MB DDR2-533 Samsung K4T51163QB-GCD5 (8Mbit x 16 x 4bank x 2devices)

WM32	0xB4000840	0x3140060A	; mem_sdconfiga	;
WM32	0xB4000848	0xA00A000C	; mem_sdconfigb	;with BB=1 to block LCD/MAE during init
WM32	0xB4000800	0x01272224	; mem_sdmode0	;CS0 mode configuration
WM32	0xB4000808	0x01272224	; mem_sdmode1	;CS1 mode configuration
WM32	0xB4000820	0x231003E0	; mem_sdaddr0	;CS0 address, 128MB at 0xa0000000
WM32	0xB4000828	0x231083E0	; mem_sdaddr1	;CS1 address, 128MB at 0xa8000000
WM32	0xB4000848	0xA00A008C	; mem_sdconfigb	;with BA=1 to temporarily block accesses
WM32	0xB40008C0	0x00000000	; mem_sdprecmd	;Precharge all banks
WM32	0xB4000880	0xC0000000	; mem_sdwrmd0	;CS0 set extended mode register 3
WM32	0xB4000888	0xC0000000	; mem_sdwrmd1	;CS1 set extended mode register 3
WM32	0xB4000880	0x80000000	; mem_sdwrmd0	;CS0 set extended mode register 2
WM32	0xB4000888	0x80000000	; mem_sdwrmd1	;CS1 set extended mode register 2
WM32	0xB4000880	0x40000440	; mem_sdwrmd0	;CS0 set extended mode register 1
WM32	0xB4000888	0x40000440	; mem_sdwrmd1	;CS1 set extended mode register 1
WM32	0xB4000880	0x00000532	; mem_sdwrmd0	;CS0 set normal mode register DLL reset
WM32	0xB4000888	0x00000532	; mem_sdwrmd1	;CS1 set normal mode register DLL reset
WM32	0xB4000848	0xA00A008C	; mem_sdconfigb	;with BA=1 to temporarily block accesses
WM32	0xB40008C0	0x00000000	; mem_sdprecmd	;Precharge all banks
WM32	0xB40008c8	0x00000000	; mem_sdautoref	;Issue two auto refreshes
WM32	0xB40008c8	0x00000000	; mem_sdautoref	;Issue two auto refreshes
WM32	0xB4000880	0x00000432	; mem_sdwrmd0	;CS0 set normal mode register
WM32	0xB4000888	0x00000432	; mem_sdwrmd1	;CS1 set normal mode register
WM32	0xB4000840	0xB140060A	; mem_sdconfiga	;Enable refresh
WM32	0xB4000848	0xA002000C	; mem_sdconfigb	;with BB=0 to allow LCD/MAE

; Setup TLB
;WTLB	0x00000600	0x01F80017	;System Flash 2 x 4MB, uncached DVG

; Invalidate Caches
;IVIC	4			128			;Invalidate IC, 4 way, 128 sets
;IVDC	4			128			;Invalidate DC, 4 way, 128 sets

[TARGET]
JTAGCLOCK	0					;use 16 MHz JTAG clock
CPUTYPE		AU1000				;the used target CPU type
ENDIAN		LITTLE				;target is little endian
STARTUP		STOP 5000			;STOP mode is used to let the monitor init the system
RESET		JTAG				;the reset type (NONE, JTAG, HARD)
WORKSPACE	0xA0100000			;workspace in target RAM for fast download
BDIMODE		AGENT				;the BDI working mode (LOADONLY | AGENT)
BREAKMODE	SOFT				;SOFT or HARD, HARD uses PPC hardware breakpoints
STEPMODE	JTAG				;JTAG, HWBP or SWBP
VECTOR		CATCH				;catch unhandled exceptions

[HOST]
IP		163.181.62.41
FILE		yamon-02.27GDB1200.rec.m	;file loaded via load
FORMAT		SREC
LOAD		MANUAL				;load code MANUAL or AUTO after reset

[FLASH]
CHIPTYPE	MIRRORX16;
CHIPSIZE	0X02000000;			;32MB each
BUSWIDTH	16;
FILE		yamon-02.27GDB1200.rec.m	;file loaded via prog
FORMAT		SREC;
;WORKSPACE	0xA0100000;
ERASE		0xBFC00000;
ERASE		0xBFC10000;
ERASE		0xBFC20000;
ERASE		0xBFC30000;
ERASE		0xBFC40000;
ERASE		0xBFC50000;
ERASE		0xBFC60000;
ERASE		0xBFC70000;
ERASE		0xBFC80000;
ERASE		0xBFC90000;
ERASE		0xBFCA0000;
ERASE		0xBFCB0000;
ERASE		0xBFCC0000;
ERASE		0xBFCD0000;
ERASE		0xBFCE0000;
ERASE		0xBFCF0000;

[REGS]
DMM1	0xB4000000				;memory controller base address
DMM2	0xB0400000				;interrupt controller 0 base address
DMM3	0xB1800000				;interrupt controller 1 base address
FILE	C:\Work\tftpsrv\BDI2000\regau1k.def
;FILE	C:\Work\EJTAG\BDI2000\regau1k.def