rom2.vhd

vhdl rom 程序

-- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_rom 

-- ============================================================
-- File Name: rom.vhd
-- Megafunction Name(s):
-- 			lpm_rom
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************


--	Copyright (C) 1988-2000 Altera Corporation

--	Any megafunction design, and related net list (encrypted or decrypted),
--	support information, device programming or simulation file, and any other
--	associated documentation or information provided by Altera or a partner
--	under Altera's Megafunction Partnership Program may be used only to
--	program PLD devices (but not masked PLD devices) from Altera.  Any other
--	use of such megafunction design, net list, support information, device
--	programming or simulation file, or any other related documentation or
--	information is prohibited for any other purpose, including, but not
--	limited to modification, reverse engineering, de-compiling, or use with
--	any other silicon devices, unless such use is explicitly licensed under
--	a separate agreement with Altera or a megafunction partner.  Title to
--	the intellectual property, including patents, copyrights, trademarks,
--	trade secrets, or maskworks, embodied in any such megafunction design,
--	net list, support information, device programming or simulation file, or
--	any other related documentation or information provided by Altera or a
--	megafunction partner, remains with Altera, the megafunction partner, or
--	their respective licensors.  No other licenses, including any licenses
--	needed under any third party's intellectual property, are provided herein.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY rom2 IS
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END rom2;


ARCHITECTURE SYN OF rom2 IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);



	COMPONENT rom_256x16 
   PORT (address: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		inclock: IN STD_LOGIC ;
		outclock: IN STD_LOGIC;
		memenab: IN STD_LOGIC := '1';
		q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
	--PORT (

		--	address	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		--	inclock	: IN STD_LOGIC ;
		--	q	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
--	);
	END COMPONENT;

attribute black_box: boolean;
attribute LPM_WIDTH: POSITIVE;
attribute LPM_WIDTHAD: POSITIVE;
attribute LPM_TYPE: string;
attribute LPM_FILE: string;


attribute black_box of rom_256x16: component is true;
attribute LPM_WIDTH of rom_256x16: component is 16;
attribute LPM_WIDTHAD of rom_256x16: component is 8; 
-- Here is where we specify that the LPM parameterized module we
--    want to use is:  "LPM_RAM_DQ"
attribute LPM_TYPE of rom_256x16: component is "LPM_ROM";
attribute LPM_FILE OF  rom_256x16:component is "F:/123/50rom.mif";
--

	

BEGIN
	q    <= sub_wire0(15 DOWNTO 0);

--	rom_6x6 : lpm_rom
 
 	 
I1:	rom_256x16 PORT MAP (
		address => address,
		inclock => inclock,
		OUTCLOCK=>inclock,
		MEMENAB=>'1',
		q => sub_wire0
	);



END SYN;