rtl_file_list.lst

这是ethernet的VHDL实现 OpenIPCore

../../../../rtl/verilog/eth_crc.v
../../../../rtl/verilog/eth_defines.v
../../../../rtl/verilog/eth_maccontrol.v
../../../../rtl/verilog/eth_macstatus.v
../../../../rtl/verilog/eth_miim.v
../../../../rtl/verilog/eth_outputcontrol.v
../../../../rtl/verilog/eth_random.v
../../../../rtl/verilog/eth_receivecontrol.v
../../../../rtl/verilog/eth_register.v
../../../../rtl/verilog/eth_registers.v
../../../../rtl/verilog/eth_rxcounters.v
../../../../rtl/verilog/eth_rxethmac.v
../../../../rtl/verilog/eth_rxstatem.v
../../../../rtl/verilog/eth_shiftreg.v
../../../../rtl/verilog/timescale.v
../../../../rtl/verilog/eth_top.v
../../../../rtl/verilog/eth_transmitcontrol.v
../../../../rtl/verilog/eth_txcounters.v
../../../../rtl/verilog/eth_txethmac.v
../../../../rtl/verilog/eth_txstatem.v
../../../../rtl/verilog/eth_clockgen.v
../../../../rtl/verilog/eth_spram_256x32.v
../../../../rtl/verilog/eth_wishbone.v
../../../../rtl/verilog/eth_fifo.v
../../../../rtl/verilog/eth_rxaddrcheck.v