run proc ts control.vhd

protel电路设计教程

---------------------------------------------------
-- Module Run Processor TS Control
-- Feburary 21, 1999
-- "Copyright (c) 2001 Altium Limited"
---------------------------------------------------

------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.all;
Entity RUNPROC Is Port
   (
     CLK            : In    std_logic;
     F2RAMD         : In    std_logic_vector(15 downto 0);
     StartAddr      : In    std_logic_vector(20 downto 15);
     F2RAMCS        : In    std_logic_vector(3 downto 0);
     TSDAT          : In    std_logic_vector(5 downto 0);
     TSLE           : In    std_logic;
     EPPConnect     : In    std_logic;
     reset          : In    std_logic;
     RUNMODE        : Out   std_logic;
     ProcAddress    : Out   std_logic_vector(18 downto 0);
     LoadRamAddr    : Out   std_logic_vector(1 downto 0);
     ProcRAMOE      : Out   std_logic
   );
End EPPDECODE;
------------------------------------------------------------

------------------------------------------------------------
Architecture Structure Of RUNPROC Is
--
--  Commands available in RAM
--  1 1 1 1 1 1 1 1 1
--  8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
-- | F2RAMData   | TS Data   | Screen    |
-- |             | 6 - bit   |  Data     |
-- |             | offset    |           |
--
--  The return value will be a 16 bit value with the following characteristics.
-- Low order bits command sequence.
-- XXXX XXXX XXXX 1010   - New Picture to be loaded
-- XXXX XXXX XXXX 0110   - RF Command
-- XXXX XXXX XXXX 0111   - IR Command
-- XXXX XXXX XXXX 0101   - JMP to new mem location
    type state_machine is (TSIdle, TSTouched,
            TSGetCommand, TSReadRam0,
            TSChangeStartAddress, TSCSA0, TSCSA1, TSCSA2,
            TSSendRFSignal,
            TSSendIRSignal
            );

-- Component Declarations

-- Signal Declarations

signal present_state, next_state: state_machine;
signal Count6Bit : std_logic_vector(5 downto 0);
signal  : std_logic;
signal  : std_logic;
signal  : std_logic;

Begin

   RUNMODE <= not EPPConnect;
   CLOCK: process (reset, CLK)
   begin
     if reset = '1' then
        present_state <= TSIDLE;
        Count6Bit <= '000000';
     elsif rising_edge(CLK) then
        present_state <= next_state;
     end if;
   end process;


   registers: process(reset, CLK)
   begin
     case present_state is
            when TSIDLE =>
                if TSLE = '1' then
                    next_state <= TSTouched;
            --  if RFReceiveIntr = '1' Then
            --      next_state <= ReadRFData;
                else
                    next_state <= TSIDLE;
                end if;
            when TSTouched =>
                ProcAddress(0)  <= Count6Bit(0);
                ProcAddress(1)  <= Count6Bit(1);
                ProcAddress(2)  <= Count6Bit(2);
                ProcAddress(3)  <= Count6Bit(3);
                ProcAddress(4)  <= Count6Bit(4);
                ProcAddress(5)  <= Count6Bit(5)
                ProcAddress(6)  <= TSDAT(0);
                ProcAddress(7)  <= TSDAT(1);
                ProcAddress(8)  <= TSDAT(2);
                ProcAddress(9)  <= TSDAT(3);
                ProcAddress(10) <= TSDAT(4);
                ProcAddress(11) <= TSDAT(5);
                ProcAddress(12) <= StartAddr(15);
                ProcAddress(13) <= StartAddr(16);
                ProcAddress(14) <= StartAddr(17);
                ProcAddress(15) <= StartAddr(18);
                ProcAddress(16) <= StartAddr(19);
                ProcAddress(17) <= F2RAMCS(1) or F2RAMCS(3);
                ProcAddress(18) <= F2RAMCS(2) or F2RAMCS(3);
                if TSLE = '0' then
                  next_state = TSGetCommand;
                else
                  next_state = TSTouched;
                end if;
            when TSGetCommand =>
                ProcRAMOE <= '1';
                next_state <= TSReadRam0;
            when TSReadRam0 =>
                ProcRAMOE <= '1';
                If F2RAMD(3) = '1' Then
                -- Change The Picture on the Display
                  next_state <= TSChangeStartAddress;
                elsif F2RAMD(0) = '0' and F2RAMD(1) = '1' and F2RAMD(2) = '1' then
                -- Send RF Command
                  next_state <= TSSendRFSignal;
                elsif F2RAMD(0) = '1' and F2RAMD(1) = '1' and F2RAMD(2) = '1' then
                -- Send IR Command
                  next_state <= TSSendIRSignal;
                else
                  next_state <= TSIDLE
                end if;
            when TSChangeStartAddress =>
                ProcRAMOE <= '1';
                LoadRamAddress(0) <= '1';
                LoadRamAddress(1) <= '0';
                next_state <= TSCSA0;
            when TSCSA0 =>
                Count6Bit = Count6Bit + 1;
                next_state <= TSCSA1;
            when TSCSA1 =>
                ProcAddress(0) <= Count6Bit(0);
                ProcAddress(1) <= Count6Bit(1);
                ProcAddress(2) <= Count6Bit(2);
                ProcAddress(3) <= Count6Bit(3);
                ProcAddress(4) <= Count6Bit(4);
                ProcAddress(5) <= Count6Bit(5);
                next_state <= TSCSA2;
            when TSCSA2 =>
                ProcRAMOE <= '1';
                next_state <= TSCSA3;
            when TSCSA3 =>
                ProcRAMOE <= '1';
                LoadRamAddress(0) <= '1';
                LoadRamAddress(1) <= '1';
                next_state <= TSIDLE;
            when TSSendRFSignal =>
            --  Load the message and control signal to be send out(Analog circuitry will
            --   boost this up to either the 27MHz, 40MHz or 300MHz plug in transmitter cards)
                next_state <= TSIDLE;
            when TSSendRFSignal =>
            --  Load the PWM IR Command in to the Shift register and send signal 9600.
                next_state <= TSIDLE;
            end case;
    end process;

End;