epp decoder.vhd

protel电路设计教程

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-- Module <Name>
-- <Date> - <Time>
--  etc...
-- "Copyright (c) 2001 Altium Limited"
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Library ieee;
Use ieee.std_logic_1164.all;
Entity EPPDECODE Is Port
   (
     CLK           : In    std_logic;
     EPPRESET      : In    std_logic;
     EPPWRITE      : In    std_logic;
     EPPDATASTB    : In    std_logic;
     EPPADDRSTB    : In    std_logic;
     EPPDATA       : InOut std_logic_vector(7 downto 0);
     EPPINTERRUPT  : Out   std_logic;
     EPPWAIT       : Out   std_logic;
     EPPSPARE      : Out   std_logic_vector(2 downto 0);
     ProgScreenRam : Out   std_logic;
     LoadReg       : Out   std_logic_vector(2 downto 0)
   );
End EPPDECODE;
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Architecture Structure Of EPPDECODE Is
--  EPPDW EPP Data Write
--  EPPAW EPP Addr Write - This contains the Instruction set for the programming of the ram
--  EPPDR EPP Data Read - Currently Not Implimented
--  EPPAR EPP Data Read - Currently Not Implimented
    type state_machine is (EPPIdle,
            EPPDWBegin, EPPDWWait, EPPDWGetData, EPPDWUseData, EPPDWDone,
            EPPAWBegin, EPPAWWait, EPPAWGetData, EPPAWUseData, EPPAWDone,
            EPPDRBegin, EPPDRPlaceData, EPPDRWait, EPPDRDone,
            EPPARBegin, EPPARPlaceData, EPPARWait, EPPARDone);
    signal present_state, next_state: state_machine;

-- Component Declarations

-- Signal Declarations

signal reset : std_logic;
signal DataStb : std_logic;
signal AddrStb : std_logic;
signal swait    : std_logic;
signal write   : std_logic;

Begin

  reset <= not EPPRESET;
  DataStb <= not EPPDATASTB;
  AddrStb <= not EPPADDRSTB;
  EPPWAIT <= not swait;
  write   <= not EPPWRITE;

    registers: process(reset,clk)
    begin
        if reset = '1' then
            present_state <= EPPIdle;
        elsif rising_edge(clk) then
          if present_state = EPPIdle then
            if (DataStb AND write) = '1' then
               present_state <= EPPDWBegin;
            elsif (AddrStb AND write) = '1' then
               present_state <= EPPAWBegin;
            elsif (DataStb AND not write) = '1' then
               present_state <= EPPDRBegin;
            elsif (AddrStb AND not write) = '1' then
               present_state <= EPPARBegin;
            end if;
          elsif present_state = EPPDWBegin then
            present_state <= EPPDWWait;
            swait <= '1';

          end if;
        end if;
    end process registers;


End Structure;
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