screen data read.vhd

protel电路设计教程

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-- Module Screen Data Read
-- Feb 18 1999
-- "Copyright (c) 2001 Altium Limited"
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Library ieee;
Use ieee.std_logic_1164.all;

Entity RamRead Is Port
   (
     CLK           : In    std_logic;
     Enable        : In    std_logic;
     vpixel        : In    std_logic_vector(1 downto 0);  -- Is either 1, 2 or 3 for the line
     HorzCount     : In    std_logic_vector(8 downto 0);
     VertCount     : In    std_logic_vector(7 downto 0);
     redout        : Out   std_logic_vector(3 downto 0);
     blueout       : Out   std_logic_vector(3 downto 0);
     greenout      : Out   std_logic_vector(3 downto 0);
     FRAMA         : Out   std_logic_vector(14 downto 0);
     FRAMD         : In    std_logic_vector(7 downto 0);
     FRAMOE        : Out   std_logic;
     ScreenEnable  : Out   std_logic
   );
End RamRead;
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use work.Quantize.all;
Architecture Structure Of RamRead Is

-- Signal Declarations

Signal LoadAddress  : std_logic;
Signal ShiftAddress : std_logic;
Signal EnableFramCE : std_logic;
Signal EnableFramOE : std_logic;
Signal red   : std_logic_vector(3 downto 0);
Signal blue  : std_logic_vector(3 downto 0);
Signal green : std_logic_vector(3 downto 0);
Signal hpixel: std_logic_vector(1 downto 0);
Begin
    process(Clk)
        variable Q      : integer range 0 to 3;
        variable hcount : integer range 1 to 3;
    begin
        hpixel <= to_vector(1,hcount);
        if enable = '0' then                -- Asynchronous reset
            Q := 0;
            hcount := 1;
            ScreenEnable <= '0';
        elsif rising_edge(Clk) then
            ScreenEnable <= '1';
            FRAMOE <= '1';
            if Q := 3 Then
              redout   <= DeQuantize9(  red, hpixel, vpixel);
              blueout  <= DeQuantize9( blue, hpixel, vpixel);
              greenout <= DeQuantize9(green, hpixel, vpixel);
            end if;
        elsif falling_edge(Clk) then
           -- Load the Registers
            ScreenEnable <= '1';
            FRAMOE <= '1';
            if    Q = 0 then
                LoadRegisters(red, FRAMD) <= '1';
                Q := 1;
            elsif Q = 1 then
                LoadRegisters(blue, FRAMD) <= '1';
                Q := 2;
            elsif Q = 2 then
                LoadRegisters(green, FRAMD) <= '1';
                Q := 3;
            elsif Q = 3 then
                LoadRegisters(green, FRAMD) <= '1';
                Q := 0;
            end if;
            if    hpixel = 0 and Q = 3 Then
               hpixel = 1;
            elsif hpixel = 1 and Q = 3 Then
               hpixel = 2;
            elsif hpizel = 2 and Q = 3 Then
               hpixel = 0;
            end if
        end if;

    end process;

End Structure;
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