op.c

qemu性能直逼VMware的仿真器QEMU 的模擬速度約為實機的 25％；約為 Bochs 的 60 倍。Plex86、User-Mode-Linux、VMware 和 Virtual PC 則比

void op_drotrv (void)
{
    target_ulong tmp;

    T0 &= 0x3F;
    if (T0) {
       tmp = T1 << (0x40 - T0);
       T0 = (T1 >> T0) | tmp;
    } else
       T0 = T1;
    RETURN();
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

void op_dclo (void)
{
    int n;

    if (T0 == ~((target_ulong)0)) {
        T0 = 64;
    } else {
        for (n = 0; n < 64; n++) {
            if (!(T0 & (1ULL << 63)))
                break;
            T0 = T0 << 1;
        }
        T0 = n;
    }
    RETURN();
}

void op_dclz (void)
{
    int n;

    if (T0 == 0) {
        T0 = 64;
    } else {
        for (n = 0; n < 64; n++) {
            if (T0 & (1ULL << 63))
                break;
            T0 = T0 << 1;
        }
        T0 = n;
    }
    RETURN();
}
#endif

/* 64 bits arithmetic */
#if TARGET_LONG_BITS > HOST_LONG_BITS
void op_mult (void)
{
    CALL_FROM_TB0(do_mult);
    RETURN();
}

void op_multu (void)
{
    CALL_FROM_TB0(do_multu);
    RETURN();
}

void op_madd (void)
{
    CALL_FROM_TB0(do_madd);
    RETURN();
}

void op_maddu (void)
{
    CALL_FROM_TB0(do_maddu);
    RETURN();
}

void op_msub (void)
{
    CALL_FROM_TB0(do_msub);
    RETURN();
}

void op_msubu (void)
{
    CALL_FROM_TB0(do_msubu);
    RETURN();
}

#else /* TARGET_LONG_BITS > HOST_LONG_BITS */

static inline uint64_t get_HILO (void)
{
    return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
}

static inline void set_HILO (uint64_t HILO)
{
    env->LO = (int32_t)(HILO & 0xFFFFFFFF);
    env->HI = (int32_t)(HILO >> 32);
}

void op_mult (void)
{
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    RETURN();
}

void op_multu (void)
{
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    RETURN();
}

void op_madd (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() + tmp);
    RETURN();
}

void op_maddu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() + tmp);
    RETURN();
}

void op_msub (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() - tmp);
    RETURN();
}

void op_msubu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() - tmp);
    RETURN();
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */

#ifdef MIPS_HAS_MIPS64
void op_dmult (void)
{
    CALL_FROM_TB0(do_dmult);
    RETURN();
}

void op_dmultu (void)
{
    CALL_FROM_TB0(do_dmultu);
    RETURN();
}
#endif

/* Conditional moves */
void op_movn (void)
{
    if (T1 != 0)
        env->gpr[PARAM1] = T0;
    RETURN();
}

void op_movz (void)
{
    if (T1 == 0)
        env->gpr[PARAM1] = T0;
    RETURN();
}

#ifdef MIPS_USES_FPU
void op_movf (void)
{
    if (!(env->fcr31 & PARAM1))
        env->gpr[PARAM2] = env->gpr[PARAM3];
    RETURN();
}

void op_movt (void)
{
    if (env->fcr31 & PARAM1)
        env->gpr[PARAM2] = env->gpr[PARAM3];
    RETURN();
}
#endif

/* Tests */
#define OP_COND(name, cond) \
void glue(op_, name) (void) \
{                           \
    if (cond) {             \
        T0 = 1;             \
    } else {                \
        T0 = 0;             \
    }                       \
    RETURN();               \
}

OP_COND(eq, T0 == T1);
OP_COND(ne, T0 != T1);
OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
OP_COND(geu, T0 >= T1);
OP_COND(lt, (int32_t)T0 < (int32_t)T1);
OP_COND(ltu, T0 < T1);
OP_COND(gez, (int32_t)T0 >= 0);
OP_COND(gtz, (int32_t)T0 > 0);
OP_COND(lez, (int32_t)T0 <= 0);
OP_COND(ltz, (int32_t)T0 < 0);

/* Branches */
//#undef USE_DIRECT_JUMP

void OPPROTO op_goto_tb0(void)
{
    GOTO_TB(op_goto_tb0, PARAM1, 0);
    RETURN();
}

void OPPROTO op_goto_tb1(void)
{
    GOTO_TB(op_goto_tb1, PARAM1, 1);
    RETURN();
}

/* Branch to register */
void op_save_breg_target (void)
{
    env->btarget = T2;
    RETURN();
}

void op_restore_breg_target (void)
{
    T2 = env->btarget;
    RETURN();
}

void op_breg (void)
{
    env->PC = T2;
    RETURN();
}

void op_save_btarget (void)
{
    env->btarget = PARAM1;
    RETURN();
}

/* Conditional branch */
void op_set_bcond (void)
{
    T2 = T0;
    RETURN();
}

void op_save_bcond (void)
{
    env->bcond = T2;
    RETURN();
}

void op_restore_bcond (void)
{
    T2 = env->bcond;
    RETURN();
}

void op_jnz_T2 (void)
{
    if (T2)
        GOTO_LABEL_PARAM(1);
    RETURN();
}

/* CP0 functions */
void op_mfc0_index (void)
{
    T0 = env->CP0_Index;
    RETURN();
}

void op_mfc0_random (void)
{
    CALL_FROM_TB0(do_mfc0_random);
    RETURN();
}

void op_mfc0_entrylo0 (void)
{
    T0 = (int32_t)env->CP0_EntryLo0;
    RETURN();
}

void op_mfc0_entrylo1 (void)
{
    T0 = (int32_t)env->CP0_EntryLo1;
    RETURN();
}

void op_mfc0_context (void)
{
    T0 = (int32_t)env->CP0_Context;
    RETURN();
}

void op_mfc0_pagemask (void)
{
    T0 = env->CP0_PageMask;
    RETURN();
}

void op_mfc0_pagegrain (void)
{
    T0 = env->CP0_PageGrain;
    RETURN();
}

void op_mfc0_wired (void)
{
    T0 = env->CP0_Wired;
    RETURN();
}

void op_mfc0_hwrena (void)
{
    T0 = env->CP0_HWREna;
    RETURN();
}

void op_mfc0_badvaddr (void)
{
    T0 = (int32_t)env->CP0_BadVAddr;
    RETURN();
}

void op_mfc0_count (void)
{
    CALL_FROM_TB0(do_mfc0_count);
    RETURN();
}

void op_mfc0_entryhi (void)
{
    T0 = (int32_t)env->CP0_EntryHi;
    RETURN();
}

void op_mfc0_compare (void)
{
    T0 = env->CP0_Compare;
    RETURN();
}

void op_mfc0_status (void)
{
    T0 = env->CP0_Status;
    if (env->hflags & MIPS_HFLAG_UM)
        T0 |= (1 << CP0St_UM);
    if (env->hflags & MIPS_HFLAG_ERL)
        T0 |= (1 << CP0St_ERL);
    if (env->hflags & MIPS_HFLAG_EXL)
        T0 |= (1 << CP0St_EXL);
    RETURN();
}

void op_mfc0_intctl (void)
{
    T0 = env->CP0_IntCtl;
    RETURN();
}

void op_mfc0_srsctl (void)
{
    T0 = env->CP0_SRSCtl;
    RETURN();
}

void op_mfc0_srsmap (void)
{
    T0 = env->CP0_SRSMap;
    RETURN();
}

void op_mfc0_cause (void)
{
    T0 = env->CP0_Cause;
    RETURN();
}

void op_mfc0_epc (void)
{
    T0 = (int32_t)env->CP0_EPC;
    RETURN();
}

void op_mfc0_prid (void)
{
    T0 = env->CP0_PRid;
    RETURN();
}

void op_mfc0_ebase (void)
{
    T0 = env->CP0_EBase;
    RETURN();
}

void op_mfc0_config0 (void)
{
    T0 = env->CP0_Config0;
    RETURN();
}

void op_mfc0_config1 (void)
{
    T0 = env->CP0_Config1;
    RETURN();
}

void op_mfc0_config2 (void)
{
    T0 = env->CP0_Config2;
    RETURN();
}

void op_mfc0_config3 (void)
{
    T0 = env->CP0_Config3;
    RETURN();
}

void op_mfc0_lladdr (void)
{
    T0 = (int32_t)env->CP0_LLAddr >> 4;
    RETURN();
}

void op_mfc0_watchlo0 (void)
{
    T0 = (int32_t)env->CP0_WatchLo;
    RETURN();
}

void op_mfc0_watchhi0 (void)
{
    T0 = env->CP0_WatchHi;
    RETURN();
}

void op_mfc0_xcontext (void)
{
    T0 = (int32_t)env->CP0_XContext;
    RETURN();
}

void op_mfc0_framemask (void)
{
    T0 = env->CP0_Framemask;
    RETURN();
}

void op_mfc0_debug (void)
{
    T0 = env->CP0_Debug;
    if (env->hflags & MIPS_HFLAG_DM)
        T0 |= 1 << CP0DB_DM;
    RETURN();
}

void op_mfc0_depc (void)
{
    T0 = (int32_t)env->CP0_DEPC;
    RETURN();
}

void op_mfc0_performance0 (void)
{
    T0 = env->CP0_Performance0;
    RETURN();
}

void op_mfc0_taglo (void)
{
    T0 = env->CP0_TagLo;
    RETURN();
}

void op_mfc0_datalo (void)
{
    T0 = env->CP0_DataLo;
    RETURN();
}

void op_mfc0_taghi (void)
{
    T0 = env->CP0_TagHi;
    RETURN();
}

void op_mfc0_datahi (void)
{
    T0 = env->CP0_DataHi;
    RETURN();
}

void op_mfc0_errorepc (void)
{
    T0 = (int32_t)env->CP0_ErrorEPC;
    RETURN();
}

void op_mfc0_desave (void)
{
    T0 = env->CP0_DESAVE;
    RETURN();
}

void op_mtc0_index (void)
{
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
    RETURN();
}

void op_mtc0_entrylo0 (void)
{
    /* Large physaddr not implemented */
    /* 1k pages not implemented */
    env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
    RETURN();
}

void op_mtc0_entrylo1 (void)
{
    /* Large physaddr not implemented */
    /* 1k pages not implemented */
    env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
    RETURN();
}

void op_mtc0_context (void)
{
    env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
    RETURN();
}

void op_mtc0_pagemask (void)
{
    /* 1k pages not implemented */
    env->CP0_PageMask = T0 & 0x1FFFE000;
    RETURN();
}

void op_mtc0_pagegrain (void)
{
    /* SmartMIPS not implemented */
    /* Large physaddr not implemented */
    /* 1k pages not implemented */
    env->CP0_PageGrain = 0;
    RETURN();
}

void op_mtc0_wired (void)
{
    env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
    RETURN();
}

void op_mtc0_hwrena (void)
{
    env->CP0_HWREna = T0 & 0x0000000F;
    RETURN();
}

void op_mtc0_count (void)
{
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
    RETURN();
}

void op_mtc0_entryhi (void)
{
    target_ulong old, val;

    /* 1k pages not implemented */
    /* Ignore MIPS64 TLB for now */
    val = (int32_t)T0 & 0xFFFFE0FF;
    old = env->CP0_EntryHi;
    env->CP0_EntryHi = val;
    /* If the ASID changes, flush qemu's TLB.  */
    if ((old & 0xFF) != (val & 0xFF))
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
    RETURN();
}

void op_mtc0_compare (void)
{
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
    RETURN();
}

void op_mtc0_status (void)
{
    uint32_t val, old;

    val = (int32_t)T0 & 0xFA78FF01;
    old = env->CP0_Status;
    if (T0 & (1 << CP0St_UM))
        env->hflags |= MIPS_HFLAG_UM;
    else
        env->hflags &= ~MIPS_HFLAG_UM;
    if (T0 & (1 << CP0St_ERL))
        env->hflags |= MIPS_HFLAG_ERL;
    else
        env->hflags &= ~MIPS_HFLAG_ERL;
    if (T0 & (1 << CP0St_EXL))
        env->hflags |= MIPS_HFLAG_EXL;
    else
        env->hflags &= ~MIPS_HFLAG_EXL;
    env->CP0_Status = val;
    if (loglevel & CPU_LOG_TB_IN_ASM)
       CALL_FROM_TB2(do_mtc0_status_debug, old, val);
    CALL_FROM_TB1(cpu_mips_update_irq, env);
    RETURN();
}

void op_mtc0_intctl (void)
{
    /* vectored interrupts not implemented */
    env->CP0_IntCtl = 0;
    RETURN();
}

void op_mtc0_srsctl (void)
{
    /* shadow registers not implemented */
    env->CP0_SRSCtl = 0;
    RETURN();
}

void op_mtc0_srsmap (void)
{
    /* shadow registers not implemented */
    env->CP0_SRSMap = 0;
    RETURN();
}

void op_mtc0_cause (void)
{
    env->CP0_Cause = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);

    /* Handle the software interrupt as an hardware one, as they
       are very similar */
    if (T0 & CP0Ca_IP_mask) {
        CALL_FROM_TB1(cpu_mips_update_irq, env);
    }
    RETURN();
}

void op_mtc0_epc (void)
{
    env->CP0_EPC = (int32_t)T0;
    RETURN();
}

void op_mtc0_ebase (void)
{
    /* vectored interrupts not implemented */
    /* Multi-CPU not implemented */
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
    RETURN();
}

void op_mtc0_config0 (void)
{
#if defined(MIPS_USES_R4K_TLB)
     /* Fixed mapping MMU not implemented */
    env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
#else
    env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
#endif
    RETURN();
}

void op_mtc0_config2 (void)
{
    /* tertiary/secondary caches not implemented */
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
    RETURN();
}

void op_mtc0_watchlo0 (void)
{
    env->CP0_WatchLo = (int32_t)T0;
    RETURN();
}

void op_mtc0_watchhi0 (void)
{
    env->CP0_WatchHi = T0 & 0x40FF0FF8;
    RETURN();
}

void op_mtc0_xcontext (void)
{
    env->CP0_XContext = (int32_t)T0; /* XXX */
    RETURN();
}

void op_mtc0_framemask (void)
{
    env->CP0_Framemask = T0; /* XXX */
    RETURN();
}

void op_mtc0_debug (void)
{
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
    if (T0 & (1 << CP0DB_DM))
        env->hflags |= MIPS_HFLAG_DM;
    else
        env->hflags &= ~MIPS_HFLAG_DM;
    RETURN();
}

void op_mtc0_depc (void)
{
    env->CP0_DEPC = (int32_t)T0;
    RETURN();
}

void op_mtc0_performance0 (void)
{
    env->CP0_Performance0 = T0; /* XXX */
    RETURN();
}

void op_mtc0_taglo (void)
{
    env->CP0_TagLo = T0 & 0xFFFFFCF6;