2440init.s

s3c2440bootloader的stepldr修改版

1
    ; To reduce PLL lock time, adjust the LOCKTIME register. 
    ldr r0,=LOCKTIME
    ldr r1,=0xFFFFFF
    str r1,[r0]

    ; delay
    mov     r0, #DELAY
5   subs    r0, r0, #1
    bne     %B5

    ; Configure MPLL
    ldr r0,=MPLLCON          
    ldr r1,=((92<<12)+(1<<4)+1)       ; Fin=16.9344MHz,Fout=399.65MHz, MDIV=110, PDIV=3, SDIV=1
    str r1,[r0]

    ; delay
    mov     r0, #DELAY
5   subs    r0, r0, #1
    bne     %B5

    ;Configure UPLL
    ldr     r0, =UPLLCON          
    ldr     r1, =((56<<12)+(2<<4)+2)    ; Fin=16.9344MHz, Fout=48.00MHz, MDIV=60, PDIV=4,SDIV=2
    str     r1, [r0]

    ; delay
    mov     r0, #0x200
5   subs    r0, r0, #1
    bne     %B5

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; In S3C2440 Datasheet, it is recommended that set UPLLCON first, and then 
; set MPLLCON after 7 NOP instruction.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; :::::::::::::::::::::::::::::::::::::::::::::;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;           BEGIN: Power Management 
;  For detial see Clock & Power management in Datasheet
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
	ldr	r1, =GSTATUS2    ; Determine Booting Mode
	ldr	r10, [r1]
	tst	r10, #0x2        ; Boot is caused by wakeup reset from sleep mode
	beq	%F2              ; If not wakeup from PowerOffmode Skip MISCCR setting

 
    ; Release the SDRAM signal protection by setting MISCCR[19:17] to 0
	ldr r1, =MISCCR             ; MISCCR's Bit 17, 18, 19 -> 0
	ldr	r0, [r1]                ; I don't know why, Just fallow Sample Code.
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Modified  2006-11-29
	;bic	r0, r0, #(3 << 17)      ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
	                            ; SCLK[1:0]: SDRAM clock
	                            ; SCKE: SDRAM clock enable
	bic	r0, r0, #(7 << 17)      ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
	                            ; SCLK[1:0]: SDRAM clock
	                            ; SCKE: SDRAM clock enable
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	str	r0, [r1]


	; Configure memory control registers
	add	r0, pc, #SMRDATA - (. + 8) ; r0=pc+(#SMRDATA-(pc+8))
	ldr	r1, =BWSCON	            ; BWSCON Address
	add	r2, r0, #52	            ; End address of SMRDATA
	
loop10
	ldr	r3, [r0], #4            ; r3=r0, r0=r0+4
	str r3, [r1], #4            ; r1=r3, r1=r1+4
	cmp	r2, r0
	bne loop10

	mov r1, #0x2000
	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
loop11
	subs r1, r1, #1		        ; wait until the SelfRefresh is released.
	bne loop11

    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ;----------------------------------------------------------------------------
	;ldr		r2, =0x201000		; offset into the RAM 
	;add		r2, r2, #0x30000000	; add physical base
	;mov     pc, r2				;  & jump to StartUp address
	;nop
	;nop
	;nop
	;b .
    ;
	;b	%F3						; if wakeup from PowerOff mode goto Power-up code.
    ;
	
; Watchdog reset
2
	tst		r10, #0x4			; In case of the wake-up from Watchdog reset, 
        						;    go to SDRAM start address(0x3000_0000)
	b		%F4					; If not wakeup from Watchdog reset,
;	beq		%F4					; If not wakeup from Watchdog reset,
								;	 goto Normal Mode.

	mov	r0, #4
	str	r0, [r1]				; Clear the GSTATUS2. Because same code is located in memory address.

	; Set memory control registers
	ldr	r0, =SMRDATA
	ldr	r1, =BWSCON	; BWSCON Address
	add	r2, r0, #52	; End address of SMRDATA
loop0
	ldr	r3, [r0], #4
	str r3, [r1], #4
	cmp	r2, r0
	bne loop0

	mov r1, #256
loop1
	subs r1, r1, #1		; wait until the SelfRefresh is released.
	bne loop1

	ldr		r2, =0x200000					; offset into the RAM 
	add		r2, r2, #0x30000000				; add physical base
	mov     pc, r2							;  & jump to StartUp address
	b .

; Case of Power off reset
3
	ldr 	r1, =MISCCR         ; MISCCR's Bit 17, 18, 19 -> 0
	ldr	r0, [r1]                ; I don't know why, Just fallow Sample Code.
	bic	r0, r0, #(3 << 17)      ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
	str	r0, [r1]
; - - - - - - - - - - - - - - - - - - - - - - -
;           END: Power Management 
; :::::::::::::::::::::::::::::::::::::::::::::


4
    ; Configure memory controller
    ;ldr    r0,=SMRDATA
    add     r0, pc, #SMRDATA - (. + 8)
    ldr r1,=BWSCON  ;BWSCON Address
    add r2, r0, #52 ;End address of SMRDATA
0       
    ldr r3, [r0], #4    
    str r3, [r1], #4    
    cmp r2, r0      
    bne %B0

BringUpWinCE    
    ;Normal Boot: Clear SDRAM
    ldr r1,=SDRAM_CLEAR
    ldr r2,=SDRAM_CLEAR
    ldr r3,=SDRAM_CLEAR
    ldr r4,=SDRAM_CLEAR
    ldr r5,=SDRAM_CLEAR
    ldr r6,=SDRAM_CLEAR
    ldr r7,=SDRAM_CLEAR
    ldr r8,=SDRAM_CLEAR
1   
    ldr r9,=SDRAM_SIZE
    ldr r0,=SDRAM_BASE
0   
    stmia   r0!,{r1-r8}
    subs    r9,r9,#32 
    bne %B0

    ; Initialize stacks
    
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Added for surport USB interrupt 2005-06-01    
    ; 2006-06-01
    ;
    ; The start
    orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1		;IRQMode
	ldr	sp,=IRQStack		; IRQStack=0x33FF7000
    bic	r0,r0,#MODEMASK|NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1		;SVCMode    
	; The end
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    
    ldr sp,=SVCStack            ; r13 = 0x33ff5800
    
    
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
		ldr	r0,=HandleIRQ       ;This routine is needed
		ldr	r1,=IsrIRQ	       ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
		str	r1,[r0]
	;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	
	    
    ;Copy and paste RW data/zero initialized data
    ldr r0, =|Image$$RO$$Limit| ; r0 = pointer to ROM data (0x000009bc)
    ldr r1, =|Image$$RW$$Base|  ; r1 = RAM copy (0x33ff0000)
    ldr r3, =|Image$$ZI$$Base|  ; r3 = globals (0x33ff0004)
    
    ;Zero init base => top of initialised data
    cmp r0, r1      ; Check that they are different
    beq %F2
1       
    cmp r1, r3      ; Copy init data
    ldrcc   r2, [r0], #4    ;--> LDRCC r2, [r0] + ADD r0, r0, #4         
    strcc   r2, [r1], #4    ;--> STRCC r2, [r1] + ADD r1, r1, #4
    bcc %B1
2       
    ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
    mov r2, #0
3       
    cmp r3, r1      ; Zero init
    strcc   r2, [r3], #4
    bcc %B3

    b   Main

    LTORG

SMRDATA DATA
; Memory configuration should be optimized for best performance 
; The following parameter is not optimized.                     
; Memory access cycle parameter strategy
; 1) The memory settings is  safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz. 

        DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
        DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
        DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1 
        DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
        DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
        DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
        DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
        DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))                                                        ;GCS6
        DCD ((B7_MT<<15)+(B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
        DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
        
        DCD 0x32            ;SCLK power saving mode, BANKSIZE 128M/128M
        DCD 0x30            ;MRSR6 CL=3clk
        DCD 0x30            ;MRSR7

        ALIGN


        AREA RamData, DATA, READWRITE

        ^   _ISR_STARTADDRESS
HandleReset     #   4
HandleUndef     #   4
HandleSWI       #   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved  #   4
HandleIRQ       #   4
HandleFIQ       #   4

;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
HandleEINT0     #   4
HandleEINT1     #   4
HandleEINT2     #   4
HandleEINT3     #   4
HandleEINT4_7   #   4
HandleEINT8_23  #   4
HandleRSV6      #   4
HandleBATFLT    #   4
HandleTICK      #   4
HandleWDT       #   4
HandleTIMER0    #   4
HandleTIMER1    #   4
HandleTIMER2    #   4
HandleTIMER3    #   4
HandleTIMER4    #   4
HandleUART2     #   4
HandleLCD       #   4
HandleDMA0      #   4
HandleDMA1      #   4
HandleDMA2      #   4
HandleDMA3      #   4
HandleMMC       #   4
HandleSPI0      #   4
HandleUART1     #   4
HandleRSV24     #   4
HandleUSBD      #   4
HandleUSBH      #   4
HandleIIC       #   4
HandleUART0     #   4
HandleSPI1      #   4
HandleRTC       #   4
HandleADC       #   4

        END