2440init.s

s3c2440bootloader的stepldr修改版

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;                                                                     
; Module Name: 2440init.s                                           
; 
; Start up code for NAND bootloader. 
;
;      
;=========================================
; NAME: 2440INIT.S
; DESC: C start up codes
;       Configure memory, ISR ,stacks
;   Initialize C-variables
; HISTORY:
; 2002.02.25:kwtark: ver 0.0
; 2002.03.20:purnnamu: Add some functions for testing STOP,POWER_OFF mode
;=========================================

    INCLUDE option.inc
    INCLUDE memcfg.inc
    INCLUDE s2440addr.inc
    
    GBLL    NOT_MIN_CODE
NOT_MIN_CODE SETL  {FALSE}


BIT_SELFREFRESH EQU (1<<22)

;Pre-defined constants
USERMODE    EQU     0x10
FIQMODE     EQU     0x11
IRQMODE     EQU     0x12
SVCMODE     EQU     0x13
ABORTMODE   EQU     0x17
UNDEFMODE   EQU     0x1b
MODEMASK    EQU     0x1f
NOINT       EQU     0xc0

SDRAM_CLEAR EQU     0x0
SDRAM_TEST  EQU     0x12345678

DELAY       EQU     0x200

;The location of stacks
UserStack   EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ 
SVCStack    EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~ // 256 byte stack
UndefStack  EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack  EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack    EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack    EQU (_STACK_BASEADDRESS-0x0)    ;0x33ff8000 ~ 



;-------------------------------------------------------------------------------------------
;_FCLK   EQU (406)
;-------------------------------------------------------------------------------------------
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

R1_iA   EQU (1<<31)
R1_nF   EQU (1<<30)

; :::::::::::::::::::::::::::::::::::::::::::::
;           BEGIN: Power Management 
; - - - - - - - - - - - - - - - - - - - - - - -
Mode_USR            EQU     0x10
Mode_FIQ            EQU     0x11
Mode_IRQ            EQU     0x12
Mode_SVC            EQU     0x13
Mode_ABT            EQU     0x17
Mode_UND            EQU     0x1B
Mode_SYS            EQU     0x1F

I_Bit               EQU     0x80
F_Bit               EQU     0x40
; - - - - - - - - - - - - - - - - - - - - - - -
;           END: Power Management 
; :::::::::::::::::::::::::::::::::::::::::::::


;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
    GBLL    THUMBCODE
    [ {CONFIG} = 16 
THUMBCODE SETL  {TRUE}
        CODE32
        |   
THUMBCODE SETL  {FALSE}
        ]

        MACRO
    MOV_PC_LR
        [ THUMBCODE
            bx lr
        |
            mov pc,lr
        ]
    MEND

        MACRO
    MOVEQ_PC_LR
        [ THUMBCODE
            bxeq lr
        |
            moveq pc,lr
        ]
    MEND

        MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
    sub     sp,sp,#4        ; decrement sp(to store jump address)
    stmfd   sp!,{r0}        ; PUSH the work register to stack(lr does't push because it return to original address)
    ldr     r0,=$HandleLabel; load the address of HandleXXX to r0
    ldr     r0,[r0]         ; load the contents(service routine start address) of HandleXXX
    str     r0,[sp,#4]      ; store the contents(ISR) of HandleXXX to stack
    ldmfd   sp!,{r0,pc}     ; POP the work register and pc(jump to ISR)

    MEND


    IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
    IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise
    IMPORT  |Image$$ZI$$Base|   ; Base and limit of area
    IMPORT  |Image$$ZI$$Limit|  ; to zero initialise
    
    IMPORT  Main    ; The main entry of mon program

    AREA Init, CODE, READONLY

    ENTRY 

    ;1)The code, which converts to Big-endian, should be in little endian code.
    ;2)The following little endian code will be compiled in Big-Endian mode. 
    ;  The code byte order should be changed as the memory bus width.
    ;3)The pseudo instruction,DCD can't be used here because the linker generates error.
    ASSERT  :DEF:ENDIAN_CHANGE
    
    b   ResetHandler    ; 0x00 Reset
    b   .               ; 0x04 Undefined
    b   .               ; 0x08 Supervisor
    b   .               ; 0x0c Prefetch Abort
    b   .               ; 0x10 Data Abort
    b   .               ; 0x14 Reserved
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Added for surport USB interrupt 
    ;
    ; The start
    ;b   .               ; 0x18 IRQ    
    b   HandlerIRQ       ; 0x18 IRQ
    ; The end
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    b   .               ; 0x1C FIQ
    
PowerHandler
	str r1, [r0]		; Enable SDRAM self-refresh
	str	r3, [r2]		; MISCCR Setting
	str r5, [r4]		; Power Off !!
	b   .
    
    LTORG   
    
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Added for surport USB interrupt 
;
; The start
HandlerIRQ      HANDLER HandleIRQ


IsrIRQ
	sub	sp,sp,#4       ;reserved for PC
	stmfd	sp!,{r8-r9}

	ldr	r9,=INTOFFSET
	ldr	r9,[r9]
	ldr	r8,=HandleEINT0
	str	r8,[sp,#8]
	ldmfd	sp!,{r8-r9,pc}   
; The end
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ENTRY  
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
ResetHandler
	; Turn off bakclight of TFT LCD
    ldr    r0, =GPBCON
    ldr r1, =0x04
    str    r1, [r0]
    
	ldr 	r0, =GPBUP
	ldr	r1, =0x0
	str 	r1, [r0]	
	
	ldr 	r0, =GPBDAT
	ldr	r1, =0x00
	str 	r1, [r0]    
    
    ; Power off of TFT LCD
    ldr    r0, =GPGCON
    ldr r1, =0x100
    str    r1, [r0]
    
	ldr 	r0, =GPGUP
	ldr	r1, =0x0
	str 	r1, [r0]	
	
	ldr 	r0, =GPHDAT
	ldr	r1, =0x00
	str 	r1, [r0]
		
    ; Turn on LEDs of keyboard and then turn off
	ldr 	r0, =GPHCON
	ldr	r1, =0x04
	str 	r1, [r0]

	ldr 	r0, =GPHUP
	ldr	r1, =0x0
	str 	r1, [r0]	
	
	ldr 	r0, =GPHDAT
	ldr	r1, =0x02
	str 	r1, [r0]

	ldr	r0, =0x2000
18	subs 	r0, r0, #1
	bne	%B18
	
	ldr 	r0, =GPHDAT
	ldr	r1, =0x0
	str 	r1, [r0]
	

    ; Initialize registers of S3C2440A
    ldr r0,=WTCON       ; Watch dog disable, base address is 0x53000000
    ldr r1,=0x0
    str r1,[r0]

    ldr r0,=INTMSK      ; Interrupt mask control register, base address is 0x4a000008
    ldr r1,=0xFFFFFFFF  ; Disable all interrupt
    str r1,[r0]

    ldr r0,=INTSUBMSK   ; Interrupt sub mask register,
                        ; base address is 0x4A00001C

    ldr r1, =0x7FFF     ; Disable all sub interrupt
    str r1,[r0]

    ; CLKDIVN, FCLK:HCLK:PCLK = 1:4:8
    ldr r0,=CLKDIVN
    ldr r1,=0x5         ; FCLK:HCLK:PCLK=1:3:6
                        ; 0x0=1:1:1, 0x1=1:1:2, 0x2=1:2:2, 0x3=1:2:4, 
                        ; 0x4=1:4:4, 0x5=1:4:8, 0x6=1:3:3, 0x7=1:3:6
                        ; DIV_UPLL=0x0, set UCLK=UPLL Clock
                        ; HDIVN=0x3, set HCLK=FCLK/3, 
                        ; PDIVN=0x1, set PCLK=HCLK/2=FCLK/6
    str r1,[r0]

    ; BATT_FLT
    ldr		r1, =MISCCR
    ldr		r0, [r1]
    bic		r0, r0, #(7<<20)        ; Bit clear
    orr		r0, r0, #(4<<20)        ; MISCCR[22:20]=100
    str		r0, [r1]    

    ; Delay
    mov  r0, #DELAY     ; r0=#DELAY=0x200
5   subs r0, r0, #1     ; r0=r0-1
    bne  %B5            ; local label 5

    ; MMU_SetAsyncBusMode FCLK:HCLK= 1:2
    ands r1, r1, #0x2   ; 
    beq %F1
    mrc p15, 0, r0, c1, c0, 0
    orr r0, r0, #R1_nF:OR:R1_iA
    mcr p15, 0, r0, c1, c0, 0
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ;---------------------------------------------------------------------------------
    mov 	pc, lr
    ;---------------------------------------------------------------------------------
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;