📄 mcuinit.dbg
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;** ###################################################################
;** This code is generated by the Device Initialization Tool.
;** It is overwritten during code generation.
;** USER MODIFICATION ARE PRESERVED ONLY INSIDE INTERRUPT SERVICE ROUTINES
;**
;** Project : asdf
;** Processor : MC68HC908JL16CFJE
;** Version : Bean 01.046, Driver 01.00, CPU db: 2.87.069
;** Datasheet : MC68HC908JL16 Rev. 1.1 11/2005
;** Date/Time : 2007-4-29, 10:52
;** Abstract :
;** This bean "MC68HC908JL16_32FA" provides initialization of the
;** CPU core and shared peripherals.
;** Settings :
;** Clock setting
;** External clock : 9.8306 MHz
;** CPU mode selection : 0
;** Initialization interrupt priority : 0
;** Stop instruction enabled : no
;** LVI module : no
;**
;** Source clock : Main clock frequency / 1
;** Internal bus clock : 2.45765 MHz
;** Contents :
;** Function "MCU_init" initializes selected peripherals
;**
;** (c) Copyright UNIS, spol. s r.o. 1997-2006
;** UNIS, spol s r.o.
;** Jundrovska 33
;** 624 00 Brno
;** Czech Republic
;** http : www.processorexpert.com
;** mail : info@processorexpert.com
;** ###################################################################
INCLUDE MC68HC908JL16.inc ; I/O map for MC68HC908JL16CFJE
; Based on CPU DB MC68HC908JL16_32SP, version 2.87.071 (RegistersPrg V2.06)
; ###################################################################
; Filename : MC68HC908JL16.inc
; Processor : MC68HC908JL16CSPE
; FileFormat: V2.06
; DataSheet : MC68HC908JL16 Rev. 1.1 11/2005
; Compiler : CodeWarrior compiler
; Date/Time : 26.04.2006, 11:14
; Abstract :
; This header implements the mapping of I/O devices.
;
; (c) Copyright UNIS, spol. s r.o. 1997-2006
; UNIS, spol. s r.o.
; Jundrovska 33
; 624 00 Brno
; Czech Republic
; http : www.processorexpert.com
; mail : info@processorexpert.com
;
; File-Format-Revisions:
; - 14.11.2005, V2.00 :
; - Deprecated symbols added for backward compatibility (section at the end of this file)
; - 15.11.2005, V2.01 :
; - Fixed invalid instruction in macro __RESET_WATCHDOG for HCS12 family.
; - 17.12.2005, V2.02 :
; - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
; - 16.01.2006, V2.03 :
; - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
; - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
; - 08.03.2006, V2.04 :
; - Support for bit(s) names duplicated with any register name in .h header files
; - 24.03.2006, V2.05 :
; - Fixed macro __RESET_WATCHDOG for HCS12 family - address and correct write order.
; - 26.04.2006, V2.06 :
; - Absolute assembly supported (depreciated symbols are not defined)
;
; CPU Registers Revisions:
; - none
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
ROMStart: equ $0000BC00
ROMEnd: equ $0000FBFF
Z_RAMStart: equ $00000060
Z_RAMEnd: equ $000000FF
RAMStart: equ $00000100
RAMEnd: equ $0000025F
;
INT_ADC: equ $0000FFDE
INT_KBI: equ $0000FFE0
INT_SCITransmit: equ $0000FFE2
INT_SCIReceive: equ $0000FFE4
INT_SCIError: equ $0000FFE6
INT_MMIIC: equ $0000FFE8
Reserved6: equ $0000FFEA
INT_TIM2Ovr: equ $0000FFEC
INT_TIM2CH1: equ $0000FFEE
INT_TIM2CH0: equ $0000FFF0
INT_TIM1Ovr: equ $0000FFF2
INT_TIM1CH1: equ $0000FFF4
INT_TIM1CH0: equ $0000FFF6
Reserved13: equ $0000FFF8
INT_IRQ1: equ $0000FFFA
INT_SWI: equ $0000FFFC
INT_RESET: equ $0000FFFE
;
;*** PTA - Port A Data Register; 0x00000000 ***
PTA: equ $00000000 ;*** PTA - Port A Data Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTA_PTA0: equ 0 ; Port A Data Bit 0
PTA_PTA1: equ 1 ; Port A Data Bit 1
PTA_PTA2: equ 2 ; Port A Data Bit 2
PTA_PTA3: equ 3 ; Port A Data Bit 3
PTA_PTA4: equ 4 ; Port A Data Bit 4
PTA_PTA5: equ 5 ; Port A Data Bit 5
PTA_PTA6: equ 6 ; Port A Data Bit 6
PTA_PTA7: equ 7 ; Port A Data Bit 7
; bit position masks
mPTA_PTA0: equ %00000001
mPTA_PTA1: equ %00000010
mPTA_PTA2: equ %00000100
mPTA_PTA3: equ %00001000
mPTA_PTA4: equ %00010000
mPTA_PTA5: equ %00100000
mPTA_PTA6: equ %01000000
mPTA_PTA7: equ %10000000
;*** PTB - Port B Data Register; 0x00000001 ***
PTB: equ $00000001 ;*** PTB - Port B Data Register; 0x00000001 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTB_PTB0: equ 0 ; Port B Data Bit 0
PTB_PTB1: equ 1 ; Port B Data Bit 1
PTB_PTB2: equ 2 ; Port B Data Bit 2
PTB_PTB3: equ 3 ; Port B Data Bit 3
PTB_PTB4: equ 4 ; Port B Data Bit 4
PTB_PTB5: equ 5 ; Port B Data Bit 5
PTB_PTB6: equ 6 ; Port B Data Bit 6
PTB_PTB7: equ 7 ; Port B Data Bit 7
; bit position masks
mPTB_PTB0: equ %00000001
mPTB_PTB1: equ %00000010
mPTB_PTB2: equ %00000100
mPTB_PTB3: equ %00001000
mPTB_PTB4: equ %00010000
mPTB_PTB5: equ %00100000
mPTB_PTB6: equ %01000000
mPTB_PTB7: equ %10000000
;*** PTD - Port D Data Register; 0x00000003 ***
PTD: equ $00000003 ;*** PTD - Port D Data Register; 0x00000003 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTD_PTD0: equ 0 ; Port D Data Bit 0
PTD_PTD1: equ 1 ; Port D Data Bit 1
PTD_PTD2: equ 2 ; Port D Data Bit 2
PTD_PTD3: equ 3 ; Port D Data Bit 3
PTD_PTD4: equ 4 ; Port D Data Bit 4
PTD_PTD5: equ 5 ; Port D Data Bit 5
PTD_PTD6: equ 6 ; Port D Data Bit 6
PTD_PTD7: equ 7 ; Port D Data Bit 7
; bit position masks
mPTD_PTD0: equ %00000001
mPTD_PTD1: equ %00000010
mPTD_PTD2: equ %00000100
mPTD_PTD3: equ %00001000
mPTD_PTD4: equ %00010000
mPTD_PTD5: equ %00100000
mPTD_PTD6: equ %01000000
mPTD_PTD7: equ %10000000
;*** DDRA - Data Direction Register A; 0x00000004 ***
DDRA: equ $00000004 ;*** DDRA - Data Direction Register A; 0x00000004 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRA_DDRA0: equ 0 ; Data Direction Register A Bit 0
DDRA_DDRA1: equ 1 ; Data Direction Register A Bit 1
DDRA_DDRA2: equ 2 ; Data Direction Register A Bit 2
DDRA_DDRA3: equ 3 ; Data Direction Register A Bit 3
DDRA_DDRA4: equ 4 ; Data Direction Register A Bit 4
DDRA_DDRA5: equ 5 ; Data Direction Register A Bit 5
DDRA_DDRA6: equ 6 ; Data Direction Register A Bit 6
DDRA_DDRA7: equ 7 ; Data Direction Register A Bit 7
; bit position masks
mDDRA_DDRA0: equ %00000001
mDDRA_DDRA1: equ %00000010
mDDRA_DDRA2: equ %00000100
mDDRA_DDRA3: equ %00001000
mDDRA_DDRA4: equ %00010000
mDDRA_DDRA5: equ %00100000
mDDRA_DDRA6: equ %01000000
mDDRA_DDRA7: equ %10000000
;*** DDRB - Data Direction Register B; 0x00000005 ***
DDRB: equ $00000005 ;*** DDRB - Data Direction Register B; 0x00000005 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRB_DDRB0: equ 0 ; Data Direction Register B Bit 0
DDRB_DDRB1: equ 1 ; Data Direction Register B Bit 1
DDRB_DDRB2: equ 2 ; Data Direction Register B Bit 2
DDRB_DDRB3: equ 3 ; Data Direction Register B Bit 3
DDRB_DDRB4: equ 4 ; Data Direction Register B Bit 4
DDRB_DDRB5: equ 5 ; Data Direction Register B Bit 5
DDRB_DDRB6: equ 6 ; Data Direction Register B Bit 6
DDRB_DDRB7: equ 7 ; Data Direction Register B Bit 7
; bit position masks
mDDRB_DDRB0: equ %00000001
mDDRB_DDRB1: equ %00000010
mDDRB_DDRB2: equ %00000100
mDDRB_DDRB3: equ %00001000
mDDRB_DDRB4: equ %00010000
mDDRB_DDRB5: equ %00100000
mDDRB_DDRB6: equ %01000000
mDDRB_DDRB7: equ %10000000
;*** DDRD - Data Direction Register D; 0x00000007 ***
DDRD: equ $00000007 ;*** DDRD - Data Direction Register D; 0x00000007 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
DDRD_DDRD0: equ 0 ; Data Direction Register D Bit 0
DDRD_DDRD1: equ 1 ; Data Direction Register D Bit 1
DDRD_DDRD2: equ 2 ; Data Direction Register D Bit 2
DDRD_DDRD3: equ 3 ; Data Direction Register D Bit 3
DDRD_DDRD4: equ 4 ; Data Direction Register D Bit 4
DDRD_DDRD5: equ 5 ; Data Direction Register D Bit 5
DDRD_DDRD6: equ 6 ; Data Direction Register D Bit 6
DDRD_DDRD7: equ 7 ; Data Direction Register D Bit 7
; bit position masks
mDDRD_DDRD0: equ %00000001
mDDRD_DDRD1: equ %00000010
mDDRD_DDRD2: equ %00000100
mDDRD_DDRD3: equ %00001000
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