📄 application.dbg
字号:
DDRE_DDRE0: equ 0 ; Data Direction Register E Bit 0
DDRE_DDRE1: equ 1 ; Data Direction Register E Bit 1
; bit position masks
mDDRE_DDRE0: equ %00000001
mDDRE_DDRE1: equ %00000010
;*** PTAPUE - Input Pull-Up Enable Register; 0x0000000D ***
PTAPUE: equ $0000000D ;*** PTAPUE - Input Pull-Up Enable Register; 0x0000000D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTAPUE_PTAPUE0: equ 0 ; Pull-Up Enable bit 0, Port A
PTAPUE_PTAPUE1: equ 1 ; Pull-Up Enable bit 1, Port A
PTAPUE_PTAPUE2: equ 2 ; Pull-Up Enable bit 2, Port A
PTAPUE_PTAPUE3: equ 3 ; Pull-Up Enable bit 3, Port A
PTAPUE_PTAPUE4: equ 4 ; Pull-Up Enable bit 4, Port A
PTAPUE_PTAPUE5: equ 5 ; Pull-Up Enable bit 5, Port A
PTAPUE_PTAPUE6: equ 6 ; Pull-Up Enable bit 6, Port A
PTAPUE_PTA6EN: equ 7 ; Enable PTA6 on OSC2, Port A
; bit position masks
mPTAPUE_PTAPUE0: equ %00000001
mPTAPUE_PTAPUE1: equ %00000010
mPTAPUE_PTAPUE2: equ %00000100
mPTAPUE_PTAPUE3: equ %00001000
mPTAPUE_PTAPUE4: equ %00010000
mPTAPUE_PTAPUE5: equ %00100000
mPTAPUE_PTAPUE6: equ %01000000
mPTAPUE_PTA6EN: equ %10000000
;*** PTA7PUE - Input Pull-Up Enable Register; 0x0000000E ***
PTA7PUE: equ $0000000E ;*** PTA7PUE - Input Pull-Up Enable Register; 0x0000000E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTA7PUE_PTAPUE7: equ 7 ; Pull-Up Enable bit 7, Port A
; bit position masks
mPTA7PUE_PTAPUE7: equ %10000000
;*** SCC1 - SCI Control Register 1; 0x00000013 ***
SCC1: equ $00000013 ;*** SCC1 - SCI Control Register 1; 0x00000013 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCC1_PTY: equ 0 ; Parity Bit
SCC1_PEN: equ 1 ; Parity Enable Bit
SCC1_ILTY: equ 2 ; Idle Line Type Bit
SCC1_WAKE: equ 3 ; Wakeup Condition Bit
SCC1_M: equ 4 ; Mode (Character Length) Bit
SCC1_TXINV: equ 5 ; Transmit Inversion Bit
SCC1_ENSCI: equ 6 ; Enable SCI Bit
SCC1_LOOPS: equ 7 ; Loop Mode Select Bit
; bit position masks
mSCC1_PTY: equ %00000001
mSCC1_PEN: equ %00000010
mSCC1_ILTY: equ %00000100
mSCC1_WAKE: equ %00001000
mSCC1_M: equ %00010000
mSCC1_TXINV: equ %00100000
mSCC1_ENSCI: equ %01000000
mSCC1_LOOPS: equ %10000000
;*** SCC2 - SCI Control Register 2; 0x00000014 ***
SCC2: equ $00000014 ;*** SCC2 - SCI Control Register 2; 0x00000014 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCC2_SBK: equ 0 ; Send Break Bit
SCC2_RWU: equ 1 ; Receiver Wakeup Bit
SCC2_RE: equ 2 ; Receiver Enable Bit
SCC2_TE: equ 3 ; Transmitter Enable Bit
SCC2_ILIE: equ 4 ; Idle Line Interrupt Enable Bit
SCC2_SCRIE: equ 5 ; SCI Receive Interrupt Enable Bit
SCC2_TCIE: equ 6 ; Transmission Complete Interrupt Enable Bit
SCC2_SCTIE: equ 7 ; SCI Transmit Interrupt Enable Bit
; bit position masks
mSCC2_SBK: equ %00000001
mSCC2_RWU: equ %00000010
mSCC2_RE: equ %00000100
mSCC2_TE: equ %00001000
mSCC2_ILIE: equ %00010000
mSCC2_SCRIE: equ %00100000
mSCC2_TCIE: equ %01000000
mSCC2_SCTIE: equ %10000000
;*** SCC3 - SCI Control Register 3; 0x00000015 ***
SCC3: equ $00000015 ;*** SCC3 - SCI Control Register 3; 0x00000015 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCC3_PEIE: equ 0 ; Receiver Parity Error Interrupt Enable Bit
SCC3_FEIE: equ 1 ; Receiver Framing Error Interrupt Enable Bit
SCC3_NEIE: equ 2 ; Receiver Noise Error Interrupt Enable Bit
SCC3_ORIE: equ 3 ; Receiver Overrun Interrupt Enable Bit
SCC3_T8: equ 6 ; Transmitted Bit 8
SCC3_R8: equ 7 ; Received Bit 8
; bit position masks
mSCC3_PEIE: equ %00000001
mSCC3_FEIE: equ %00000010
mSCC3_NEIE: equ %00000100
mSCC3_ORIE: equ %00001000
mSCC3_T8: equ %01000000
mSCC3_R8: equ %10000000
;*** SCS1 - SCI Status Register 1; 0x00000016 ***
SCS1: equ $00000016 ;*** SCS1 - SCI Status Register 1; 0x00000016 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCS1_PE: equ 0 ; Receiver Parity Error Bit
SCS1_FE: equ 1 ; Receiver Framing Error Bit
SCS1_NF: equ 2 ; Receiver Noise Flag Bit
SCS1_OR: equ 3 ; Receiver Overrun Bit
SCS1_IDLE: equ 4 ; Receiver Idle Bit
SCS1_SCRF: equ 5 ; SCI Receiver Full Bit
SCS1_TC: equ 6 ; Transmission Complete Bit
SCS1_SCTE: equ 7 ; SCI Transmitter Empty Bit
; bit position masks
mSCS1_PE: equ %00000001
mSCS1_FE: equ %00000010
mSCS1_NF: equ %00000100
mSCS1_OR: equ %00001000
mSCS1_IDLE: equ %00010000
mSCS1_SCRF: equ %00100000
mSCS1_TC: equ %01000000
mSCS1_SCTE: equ %10000000
;*** SCS2 - SCI Status Register 2; 0x00000017 ***
SCS2: equ $00000017 ;*** SCS2 - SCI Status Register 2; 0x00000017 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCS2_RPF: equ 0 ; Reception in Progress Flag Bit
SCS2_BKF: equ 1 ; Break Flag Bit
; bit position masks
mSCS2_RPF: equ %00000001
mSCS2_BKF: equ %00000010
;*** SCDR - SCI Data Register; 0x00000018 ***
SCDR: equ $00000018 ;*** SCDR - SCI Data Register; 0x00000018 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCDR_R0_T0: equ 0 ; Receive/Transmit Data Bit 0
SCDR_R1_T1: equ 1 ; Receive/Transmit Data Bit 1
SCDR_R2_T2: equ 2 ; Receive/Transmit Data Bit 2
SCDR_R3_T3: equ 3 ; Receive/Transmit Data Bit 3
SCDR_R4_T4: equ 4 ; Receive/Transmit Data Bit 4
SCDR_R5_T5: equ 5 ; Receive/Transmit Data Bit 5
SCDR_R6_T6: equ 6 ; Receive/Transmit Data Bit 6
SCDR_R7_T7: equ 7 ; Receive/Transmit Data Bit 7
; bit position masks
mSCDR_R0_T0: equ %00000001
mSCDR_R1_T1: equ %00000010
mSCDR_R2_T2: equ %00000100
mSCDR_R3_T3: equ %00001000
mSCDR_R4_T4: equ %00010000
mSCDR_R5_T5: equ %00100000
mSCDR_R6_T6: equ %01000000
mSCDR_R7_T7: equ %10000000
;*** SCBR - SCI Baud Rate Register; 0x00000019 ***
SCBR: equ $00000019 ;*** SCBR - SCI Baud Rate Register; 0x00000019 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCBR_SCR0: equ 0 ; SCI Baud Rate Select Bit 0
SCBR_SCR1: equ 1 ; SCI Baud Rate Select Bit 1
SCBR_SCR2: equ 2 ; SCI Baud Rate Select Bit 2
SCBR_SCP0: equ 4 ; SCI Baud Rate Prescaler Bit 0
SCBR_SCP1: equ 5 ; SCI Baud Rate Prescaler Bit 1
; bit position masks
mSCBR_SCR0: equ %00000001
mSCBR_SCR1: equ %00000010
mSCBR_SCR2: equ %00000100
mSCBR_SCP0: equ %00010000
mSCBR_SCP1: equ %00100000
;*** KBSCR - Keyboard Status and Control Register; 0x0000001A ***
KBSCR: equ $0000001A ;*** KBSCR - Keyboard Status and Control Register; 0x0000001A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
KBSCR_MODEK: equ 0 ; Keyboard Triggering Sensitivity Bit
KBSCR_IMASKK: equ 1 ; Keyboard Interrupt Mask Bit
KBSCR_ACKK: equ 2 ; Keyboard Acknowledge Bit
KBSCR_KEYF: equ 3 ; Keyboard Flag Bit
; bit position masks
mKBSCR_MODEK: equ %00000001
mKBSCR_IMASKK: equ %00000010
mKBSCR_ACKK: equ %00000100
mKBSCR_KEYF: equ %00001000
;*** KBIER - Keyboard Interrrupt Enable Register; 0x0000001B ***
KBIER: equ $0000001B ;*** KBIER - Keyboard Interrrupt Enable Register; 0x0000001B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
KBIER_KBIE0: equ 0 ; Keyboard Interrupt Enable Bit 0
KBIER_KBIE1: equ 1 ; Keyboard Interrupt Enable Bit 1
KBIER_KBIE2: equ 2 ; Keyboard Interrupt Enable Bit 2
KBIER_KBIE3: equ 3 ; Keyboard Interrupt Enable Bit 3
KBIER_KBIE4: equ 4 ; Keyboard Interrupt Enable Bit 4
KBIER_KBIE5: equ 5 ; Keyboard Interrupt Enable Bit 5
KBIER_KBIE6: equ 6 ; Keyboard Interrupt Enable Bit 6
KBIER_KBIE7: equ 7 ; Keyboard Interrupt Enable Bit 7
; bit position masks
mKBIER_KBIE0: equ %00000001
mKBIER_KBIE1: equ %00000010
mKBIER_KBIE2: equ %00000100
mKBIER_KBIE3: equ %00001000
mKBIER_KBIE4: equ %00010000
mKBIER_KBIE5: equ %00100000
mKBIER_KBIE6: equ %01000000
mKBIER_KBIE7: equ %10000000
;*** INTSCR - IRQ Status and Control Register; 0x0000001D ***
INTSCR: equ $0000001D ;*** INTSCR - IRQ Status and Control Register; 0x0000001D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INTSCR_MODE: equ 0 ; IRQ Edge/Level Select Bit
INTSCR_IMASK: equ 1 ; IRQ Interrupt Mask Bit
INTSCR_ACK: equ 2 ; IRQ Interrupt Request Acknowledge Bit
INTSCR_IRQF: equ 3 ; IRQ Flag
; bit position masks
mINTSCR_MODE: equ %00000001
mINTSCR_IMASK: equ %00000010
mINTSCR_ACK: equ %00000100
mINTSCR_IRQF: equ %00001000
;*** CONFIG2 - Configuration Register 2; 0x0000001E ***
CONFIG2: equ $0000001E ;*** CONFIG2 - Configuration Register 2; 0x0000001E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CONFIG2_STOP_ICLKDIS: equ 0 ; Internal oscillator STOP mode disable bit
CONFIG2_IICSEL: equ 1 ; MMIIC Pin Selection Bit
CONFIG2_LVIT0: equ 3 ; Low Voltage Inhibit Trip Voltage Selection Bit 0
CONFIG2_LVIT1: equ 4 ; Low Voltage Inhibit Trip Voltage Selection Bit 1
CONFIG2_IRQPUD: equ 7 ; IRQ1 Pin Pull-Up Control Bit
; bit position masks
mCONFIG2_STOP_ICLKDIS: equ %00000001
mCONFIG2_IICSEL: equ %00000010
mCONFIG2_LVIT0: equ %00001000
mCONFIG2_LVIT1: equ %00010000
mCONFIG2_IRQPUD: equ %10000000
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -