📄 jflash.h
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#define LOW 0
#define HIGH 1
#define TRUE 1
#define FALSE 0
#define CORE_IDCODE 0x0F0F0F0F
#define NO_IDLE 0
#define IDLE 1
#define EXTEST 0x0
#define SCAN_N 0x2
#define INTEST 0xC
#define IDCODE 0xE
#define BYPASS 0xF
#define CLAMP 0x5
#define HIGHZ 0x7
#define CLAMPZ 0x9
#define RESTART 0x4
#define MACROCELL 0x0
#define DEBUG 0x1
#define ICE_BREAKER 0x2
#define EXTERNAL 0x3
#define ICE_DBG_CTRL 0x00
#define ICE_DBG_STS 0x01
#define ICE_DBG_COM_CTRL 0x04
#define ICE_DBG_COM_DATA 0x05
#define ICE_WTP0_ADDR_VAL 0x08
#define ICE_WTP0_ADDR_MASK 0x09
#define ICE_WTP0_DATA_VAL 0x0A
#define ICE_WTP0_DATA_MASK 0x0B
#define ICE_WTP0_CTRL_VAL 0x0C
#define ICE_WTP0_CTRL_MASK 0x0D
#define ICE_WTP1_ADDR_VAL 0x10
#define ICE_WTP1_ADDR_MASK 0x11
#define ICE_WTP1_DATA_VAL 0x12
#define ICE_WTP1_DATA_MASK 0x13
#define ICE_WTP1_CTRL_VAL 0x14
#define ICE_WTP1_CTRL_MASK 0x15
#define ICE_DBG_STS_MASK 0x0000001F //* width = 5 bits
#define READ_DEBUG_STATUS_MASK 0x9
#define R0 0x0
#define R1 0x1
#define R2 0x2
#define R3 0x3
#define R4 0x4
#define R5 0x5
#define R6 0x6
#define R7 0x7
#define R8 0x8
#define R9 0x9
#define R10 0xA
#define R11 0xB
#define R12 0xC
#define SP 0xD
#define LR 0xE
#define PC 0xF
//* Define instructions
#define NOP 0xE1A00000 // NOP
#define READ_REG 0xE58E0000 // str r0,[r14,#0]
#define WRITE_REG 0xE59E0000 // ldr r0,[r14,#0]
#define READ_MEM 0xE4901000 // ldr r1,[r0],#0
#define READ_MEM_HALFWORD 0xE0D010B0 // ldrh r1,[r0],#0
#define READ_MEM_Verify 0xE0D010B0 // ldrh r1,[r0],#-a
#define READ_MEM_Verify1 0xE0D010B0 // ldrh r2,[r0,#-8]
#define READ_MEM_Verify2 0xE0D010B0 // ldrh r3,[r0,#-6]
#define READ_MEM_Verify3 0xE0D010B0 // ldrh r4,[r0,#-4]
#define READ_MEM_Verify4 0xE0D010B0 // ldrh r5,[r0,#-2]
#define READ_MEM_Verify5 0xE0D010B0 // ldrh r6,[r0,#0]
#define READ_MEM_Verify6 0xE0D010B0 // ldrh r7,[r0,#2]
#define READ_MEM_Verify7 0xE0D010B0 // ldrh r8,[r0,#4]
#define READ_MEM_Verify8 0xE0D010B0 // ldrh r9,[r0,#6]
#define READ_MEM_Verify9 0xE0D010B0 // ldrh r10,[r0,#8]
#define READ_MEM_Verify10 0xE0D010B0 // ldrh r11,[r0,#a]
#define READ_MEM_Verify11 0xE0D010B0 // ldrh r12,[r0,#c]
#define READ_MEM_Verify12 0xE0D010B0 // ldrh r13,[r0,#e]
#define READ_MEM_Verified 0xe8b03fff // ldmia r0!,{r0-r13}
#define READ_MEM_Verified1 0xe8a000ff // stmia r0!,{r0-r7}
#define READ_MEM_Verified32 0xe8a000ff // stmia r0!,{r0-r7}
//MMU setting
#define WRITE_MMU_setting 0xee010f10 // mcr p15, 0, r0, c1, c0, 0
#define WRITE_MMU_DOMAIN_setting 0xee030f10 // mcr p15, 0, r0, c3, c0, 0
#define READ_MMU 0xee110f10 // mrc p15, 0, r0, c1, c0, 0
#define READ_CPU 0xe10f0000 // mrs r0, cpsr
#define WRITE_CPU_SET 0xe121f000 // msr cpsr_c, r0
// FLASH WRITE instructions
#define WRITE_MEM 0xE4801000 // str r1,[r0],#0
#define WRITE_MEM_HALFWORD 0xE1C010B0 // strh r1,[r0,#0]
#define WRITE_MEM_R0 0xe1c000b0 // strh r0,[r0,#0]
#define WRITE_MEM_R1 0xe14110b1 // strh r1,[r1,#-1]
#define WRITE_MEM_R2 0xe1c020b0 // strh r2,[r0,#0]
#define WRITE_MEM_W1 0xe14340b4 // strh r4,[r3,#-4]
#define WRITE_MEM_W2 0xe14350b2 // strh r5,[r3,#-2]
#define WRITE_MEM_W3 0xe1c360b0 // strh r6,[r3,#0]
#define WRITE_MEM_W4 0xe1c370b2 // strh r7,[r3,#2]
#define WRITE_MEM_W5 0xe1c380b4 // strh r8,[r3,#4]
#define WRITE_MEM_W6 0xe1c390b6 // strh r9,[r3,#6]
#define WRITE_MEM_W7 0xe1c3a0b8 // strh r10,[r3,#8]
#define WRITE_MEM_W8 0xe1c3b0ba // strh r11,[r3,#a]
#define WRITE_MEM_W9 0xe1c3c0bc // strh r12,[r3,#c]
#define WRITE_MEM_W10 0xe1c3d0be // strh r13,[r3,#e]
// FLASH Unlock WRITE instructions
#define WRITE_MEM_WR0 0xe1c000b0 // strh r0,[r0,#0]
#define WRITE_MEM_UW1 0xe14120b8 // strh r2,[r1,#-8]
#define WRITE_MEM_UW2 0xe14130b6 // strh r3,[r1,#-6]
#define WRITE_MEM_UW3 0xe14140b4 // strh r4,[r1,#-4]
#define WRITE_MEM_UW4 0xe14150b2 // strh r5,[r1,#-2]
#define WRITE_MEM_UW5 0xe1c160b0 // strh r6,[r1,#0]
#define WRITE_MEM_UW6 0xe1c170b2 // strh r7,[r1,#2]
#define WRITE_MEM_UW7 0xe1c180b4 // strh r8,[r1,#4]
#define WRITE_MEM_UW8 0xe1c190b6 // strh r9,[r1,#6]
#define WRITE_MEM_UW9 0xe1c1a0b8 // strh r10,[r1,#8]
#define WRITE_MEM_UW10 0xe1c1b0ba // strh r11,[r1,#a]
#define WRITE_MEM_UW11 0xe1c1c0bc // strh r12,[r1,#c]
#define WRITE_MEM_UW12 0xe1c1d0be // strh r13,[r1,#e]
//mode select
#define WRITE_Unlock_R0 0xe1c010b0 // strh r1,r0 MODE SELECT
#define WRITE_Unlock_R1 0xe1c230b0 // strh r3,r2
#define WRITE_Unlock_R2 0xe1c450b0 // strh r5,r4
//reset
#define WRITE_Unlock_RR0 0xe1c000b0 // strh r0,r0 RESET
#define WRITE_Unlock_RR1 0xE1C010B0 // strh r1,[r0,#0]
#define STM 0xE88E0000 // stmia r14,{}
#define LDM 0xE89E0000 // ldmia r14,{}
#define LDMIA_R0_R0_R1 0xE8900003 // ldmia r0,{r0,r1}
#define LDMIA_R0_R0_R12 0xe8901fff // ldmia r0,{r0-r12}
#define LDMIA_R0_R0_R13 0xe8903fff // ldmia r0,{r0-r13}
#define LDMIA_R0_R0_R7 0xe89000ff // ldmia r0,{r0-r7}
#define LDMIA_R0_R0_R5 0xe890003f // ldmia r0,{r0-r5}
#define LDMIA_R0_R5_R12 0xe8901fe0 // ldmia r0,{r5-r12}
#define LDMIA_R0_R3_R13 0xe8903ff8 // ldmia r0,{r3-r12}
#define LDMIA_R3_R3_R13 0xe8931ff8 // ldmia r3,{r3-r12}
#define READ_CPSR 0xE10F0000 // mrs r0,cpsr
#define WRITE_CPSR 0xE12FF000 // msr cpsr_cxsf,r0
#define BRANCH_PC_5 0xEAFFFFFB // b 0xfffffff4 ; (_end + 0xffff5d28)
#define BRANCH_PC 0xEAFFFFFF // b 0x4 ; (IMAGE_SIZE + 0x4)
#define WRITE_MEM_START 0xe890001f // ldmia r0,{r0-r4}
#define WORD 0
#define HALFWORD 1
#define WATCHDOG 100
#define ADD_WAIT_STATE 16
unsigned int JTAG_DOValue;
#define STANDARD_LPT1 0x378
#define JTAG_DEFALT 0x7fF
#define JTAG_IO_TDI 0x0001
#define JTAG_IO_TCK 0x0002
#define JTAG_IO_TMS 0x0004
#define JTAG_IO_TRST 0x0010
#define JTAG_IO_STRST 0x0020
#define JTAG_IO_RST_CTRL 0x0080
#define JTAG_IO_ACK_STRST 0x0100
#define JTAG_IO_TDO 0x10
unsigned int JTAG_Open (void);
void JTAG_Close (void);
void JTAG_prnout(void);
unsigned char JTAG_prnin (void);
void JTAG_Init (void);
void JTAG_HW_Reset(void);
void JTAG_SYS_Reset(void);
void JTAG_TCK(unsigned int state);
void JTAG_TMS(unsigned int state);
void JTAG_TDI(unsigned int state);
unsigned int JTAG_TDO(void);
void JTAG_Reset(void);
void JTAG_HW_Reset(void);
void JTAG_Shift_ir(unsigned int instruction, unsigned int idle);
void JTAG_Shift_dr_4_bits(unsigned int data);
void JTAG_IDCode(unsigned int *idcode);
void JTAG_Step(unsigned int instruction, unsigned int *data);
void JTAG_Step_System_Speed(unsigned int instruction);
void JTAG_Read_Bkru(unsigned int address, unsigned int *data);
void JTAG_Write_Bkru(unsigned int address, unsigned int data);
void JTAG_Select_Scan_Chain(unsigned int sc);
unsigned int JTAG_Read_Debug_Status(void);
unsigned int JTAG_Read_Debug_CTRL(void);
unsigned int JTAG_Test_Is_Breaked(unsigned int value);
void JTAG_Read_Memory(unsigned int address, unsigned int *value, unsigned int halfword);
void JTAG_Read_MMU(unsigned int *value);
void JTAG_CPU_SET(unsigned int address, unsigned int value, unsigned int number);
void JTAG_Read_CPU_STATUS(unsigned int *value);
void JTAG_Write_Memory(unsigned int address, unsigned int value, unsigned int halfword);
void JTAG_MMU_RESET(unsigned int address, unsigned int value, unsigned int number);
unsigned int JTAG_Stop(void);
void JTAG_Write_ICEBreaker(unsigned int address, unsigned int data);
void JTAG_Read_ICEBreaker(unsigned int address, unsigned int *data);
unsigned int Read_ID_Code(void);
void Reset(void);
void JTAG_Go(unsigned int *context);
void JTAG_Go_new(unsigned int *context);
void Flash_Write_Halfword(unsigned int vaddress, unsigned int vdata);
void Flash_Write_Halfword2(unsigned int vaddress, unsigned int vdata);
void Flash_Write2(unsigned int vaddress, unsigned int vdata);
unsigned int Flash_Read_Halfword(unsigned int vaddress);
unsigned int Flash_Read_Halfword2(unsigned int vaddress);
unsigned int Flash_Read_Word(unsigned int vaddress);
unsigned int Flash_Read_Word2(unsigned int vaddress);
int test_port(void); // Looks for and finds a valid parallel port address
void error_out(char*); // Prints error and exits program
void TestGiveIODriver();
void FoundLPT();
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