📄 c8051f320.h
字号:
/* PCA0CN 0xD8H */
sbit CCF0 = PCA0CN ^ 0; /* PCA0 MODULE 0 CAPTURE/COMPARE FLAG */
sbit CCF1 = PCA0CN ^ 1; /* PCA0 MODULE 1 CAPTURE/COMPARE FLAG */
sbit CCF2 = PCA0CN ^ 2; /* PCA0 MODULE 2 CAPTURE/COMPARE FLAG */
sbit CCF3 = PCA0CN ^ 3; /* PCA0 MODULE 3 CAPTURE/COMPARE FLAG */
sbit CCF4 = PCA0CN ^ 4; /* PCA0 MODULE 4 CAPTURE/COMPARE FLAG */
sbit CR = PCA0CN ^ 6; /* PCA0 COUNTER RUN CONTROL */
sbit CF = PCA0CN ^ 7; /* PCA0 COUNTER OVERFLOW FLAG */
/* ADC0CN 0xE8H */
sbit AD0CM0 = ADC0CN ^ 0; /* ADC0 CONVERSION MODE SELECT 0 */
sbit AD0CM1 = ADC0CN ^ 1; /* ADC0 CONVERSION MODE SELECT 1 */
sbit AD0CM2 = ADC0CN ^ 2; /* ADC0 CONVERSION MODE SELECT 2 */
sbit AD0WINT = ADC0CN ^ 3; /* ADC0 WINDOW COMPARE INTERRUPT FLAG */
sbit AD0BUSY = ADC0CN ^ 4; /* ADC0 BUSY FLAG */
sbit AD0INT = ADC0CN ^ 5; /* ADC0 CONVERISION COMPLETE INTERRUPT FLAG */
sbit AD0TM = ADC0CN ^ 6; /* ADC0 TRACK MODE */
sbit AD0EN = ADC0CN ^ 7; /* ADC0 ENABLE */
/* SPI0CN 0xF8H */
sbit SPIF = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG */
sbit WCOL = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG */
sbit MODF = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG */
sbit RXOVRN = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG */
sbit NSSMD1 = SPI0CN ^ 3; /* SPI 0 SLAVE SELECT MODE 1 */
sbit NSSMD0 = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT MODE 0 */
sbit TXBMT = SPI0CN ^ 1; /* SPI 0 TRANSMIT BUFFER EMPTY */
sbit SPIEN = SPI0CN ^ 0; /* SPI 0 SPI ENABLE */
sample2
*-------------------------------------------------------------------------
Register Declarations for the Cygnal/SiLabs C8051F32x Processor Range
Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------*/
#ifndef C8051F320_H
#define C8051F320_H
/* BYTE Registers */
__sfr __at (0x80) P0 ; /* PORT 0 */
__sfr __at (0x81) SP ; /* STACK POINTER */
__sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
__sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
__sfr __at (0x87) PCON ; /* POWER CONTROL */
__sfr __at (0x88) TCON ; /* TIMER CONTROL */
__sfr __at (0x89) TMOD ; /* TIMER MODE */
__sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
__sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
__sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
__sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
__sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
__sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
__sfr __at (0x90) P1 ; /* PORT 1 */
__sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
__sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
__sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
__sfr __at (0x96) USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
__sfr __at (0x97) USB0DAT ; /* USB0 DATA REGISTER */
__sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
__sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
__sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
__sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
__sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
__sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
__sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
__sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
__sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
__sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
__sfr __at (0xA0) P2 ; /* PORT 2 */
__sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
__sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
__sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
__sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
__sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
__sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
__sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
__sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
__sfr __at (0xB0) P3 ; /* PORT 3 */
__sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
__sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
__sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
__sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
__sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
__sfr __at (0xB9) CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
__sfr __at (0xBA) AMX0N ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
__sfr __at (0xBB) AMX0P ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
__sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
__sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
__sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
__sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
__sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
__sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
__sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
__sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
__sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
__sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
__sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
__sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
__sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
__sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
__sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
__sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
__sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
__sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
__sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
__sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
__sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
__sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
__sfr __at (0xD7) USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
__sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
__sfr __at (0xD9) PCA0MD ; /* PCA MODE */
__sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
__sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
__sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
__sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
__sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
__sfr __at (0xE0) ACC ; /* ACCUMULATOR */
__sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
__sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
__sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
__sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
__sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
__sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
__sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
__sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
__sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
__sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
__sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
__sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
__sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
__sfr __at (0xF0) B ; /* B REGISTER */
__sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE CONFIGURATION */
__sfr __at (0xF4) P3MDIN ; /* PORT 3 INPUT MODE CONFIGURATION */
__sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
__sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
__sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
__sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
__sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
__sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
__sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
__sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
__sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
__sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
/* WORD/DWORD Registers */
__sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
__sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
__sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
__sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
__sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
__sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
__sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -