📄 dtm8-td.lis
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.module dtm8-td.C
.area data(ram, con, rel)
0000 _mark::
0000 .blkb 2
.area idata
0000 DC05 .word 1500
.area data(ram, con, rel)
0002 .dbfile D:\ele\AVR\ICC\diantiao\dtm8-td\dtm8-td.C
0002 .dbsym e mark _mark I
.area text(rom, con, rel)
0000 .dbfile D:\ele\AVR\ICC\diantiao\dtm8-td\dtm8-td.C
0000 .dbfunc e port_init _port_init fV
.even
0000 _port_init::
0000 .dbline -1
0000 .dbline 32
0000 ; /******************************************/
0000 ; /* 燕山大学无线电爱好者协会 */
0000 ; /* 电子调速器 */
0000 ; /* 作者:张翃鹏 2005-2-27 9:04:40 */
0000 ; /* 目标MCU:MEGA8 晶振:INT RC 8MHZ */
0000 ; /******************************************/
0000 ;
0000 ; #include <iom8v.h>
0000 ; #include <macros.h>
0000 ; #include <eeprom.h>
0000 ; #define uchar unsigned char
0000 ; #define unit unsigned int
0000 ; #define ulong unsigned long
0000 ; #define xtal 8
0000 ; #define j11 PORTD|=0x02
0000 ; #define j10 PORTD&=~0x02
0000 ; #define j21 PORTD|=0x10
0000 ; #define j20 PORTD&=~0x10
0000 ; #define j31 PORTB|=0x40
0000 ; #define j30 PORTB&=~0x40
0000 ; #define j41 PORTD|=0x40
0000 ; #define j40 PORTD&=~0x40
0000 ; #define LED1 PORTB|=0x08;
0000 ; #define LED0 PORTB&=~0x08;
0000 ;
0000 ;
0000 ; int mark=1500;
0000 ; unit ai,aa;
0000 ; uchar i,j,az,flag,flagh,zb,mid,pwm;
0000 ;
0000 ; void port_init(void)
0000 ; {
0000 .dbline 33
0000 ; PORTB = 0x23;
0000 83E2 ldi R24,35
0002 88BB out 0x18,R24
0004 .dbline 34
0004 ; DDRB = 0x58;
0004 88E5 ldi R24,88
0006 87BB out 0x17,R24
0008 .dbline 35
0008 ; PORTC = 0x04; //m103 output only
0008 84E0 ldi R24,4
000A 85BB out 0x15,R24
000C .dbline 36
000C ; DDRC = 0x38;
000C 88E3 ldi R24,56
000E 84BB out 0x14,R24
0010 .dbline 37
0010 ; PORTD = 0x00;
0010 2224 clr R2
0012 22BA out 0x12,R2
0014 .dbline 38
0014 ; DDRD = 0x52;
0014 82E5 ldi R24,82
0016 81BB out 0x11,R24
0018 .dbline -2
0018 L1:
0018 .dbline 0 ; func end
0018 0895 ret
001A .dbend
001A .dbfunc e timer1_init _timer1_init fV
.even
001A _timer1_init::
001A .dbline -1
001A .dbline 42
001A ; }
001A ;
001A ; void timer1_init(void)
001A ; {
001A .dbline 43
001A ; TCCR1B = 0x00; //stop
001A 2224 clr R2
001C 2EBC out 0x2e,R2
001E .dbline 44
001E ; TCNT1H = 0x00 /*INVALID SETTING*/; //setup
001E 2DBC out 0x2d,R2
0020 .dbline 45
0020 ; TCNT1L = 0x00 /*INVALID SETTING*/;
0020 2CBC out 0x2c,R2
0022 .dbline 46
0022 ; OCR1AH = 0x00 /*INVALID SETTING*/;
0022 2BBC out 0x2b,R2
0024 .dbline 47
0024 ; OCR1AL = 0x00 /*INVALID SETTING*/;
0024 2ABC out 0x2a,R2
0026 .dbline 48
0026 ; OCR1BH = 0x00 /*INVALID SETTING*/;
0026 29BC out 0x29,R2
0028 .dbline 49
0028 ; OCR1BL = 0x00 /*INVALID SETTING*/;
0028 28BC out 0x28,R2
002A .dbline 50
002A ; ICR1H = 0x00 /*INVALID SETTING*/;
002A 27BC out 0x27,R2
002C .dbline 51
002C ; ICR1L = 0x00 /*INVALID SETTING*/;
002C 26BC out 0x26,R2
002E .dbline 52
002E ; TCCR1A = 0x00;
002E 2FBC out 0x2f,R2
0030 .dbline 53
0030 ; TCCR1B = 0x02; //start Timer
0030 82E0 ldi R24,2
0032 8EBD out 0x2e,R24
0034 .dbline -2
0034 L2:
0034 .dbline 0 ; func end
0034 0895 ret
0036 .dbend
0036 .dbfunc e timer2_init _timer2_init fV
.even
0036 _timer2_init::
0036 .dbline -1
0036 .dbline 57
0036 ; }
0036 ;
0036 ; void timer2_init(void)
0036 ; {
0036 .dbline 58
0036 ; TCCR2 = 0x00; //stop
0036 2224 clr R2
0038 25BC out 0x25,R2
003A .dbline 59
003A ; ASSR = 0x00; //set async mode
003A 22BC out 0x22,R2
003C .dbline 60
003C ; TCNT2 = 0x00 /*INVALID SETTING*/; //setup
003C 24BC out 0x24,R2
003E .dbline 61
003E ; OCR2 = 0x00 /*INVALID SETTING*/;
003E 23BC out 0x23,R2
0040 .dbline 62
0040 ; TCCR2 = 0x02; //start
0040 82E0 ldi R24,2
0042 85BD out 0x25,R24
0044 .dbline -2
0044 L3:
0044 .dbline 0 ; func end
0044 0895 ret
0046 .dbend
0046 .dbfunc e watchdog_init _watchdog_init fV
.even
0046 _watchdog_init::
0046 .dbline -1
0046 .dbline 66
0046 ; }
0046 ;
0046 ; void watchdog_init(void)
0046 ; {
0046 .dbline 67
0046 ; WDR(); //this prevents a timout on enabling
0046 A895 wdr
0048 .dbline 68
0048 ; WDTCR = 0x08; //WATCHDOG ENABLED - dont forget to issue WDRs
0048 88E0 ldi R24,8
004A 81BD out 0x21,R24
004C .dbline -2
004C L4:
004C .dbline 0 ; func end
004C 0895 ret
004E .dbend
004E .dbfunc e init_devices _init_devices fV
.even
004E _init_devices::
004E .dbline -1
004E .dbline 72
004E ; }
004E ;
004E ; void init_devices(void)
004E ; {
004E .dbline 73
004E ; CLI(); //disable all interrupts
004E F894 cli
0050 .dbline 74
0050 ; port_init();
0050 D7DF rcall _port_init
0052 .dbline 75
0052 ; timer1_init();
0052 E3DF rcall _timer1_init
0054 .dbline 76
0054 ; timer2_init();
0054 F0DF rcall _timer2_init
0056 .dbline 77
0056 ; watchdog_init();
0056 F7DF rcall _watchdog_init
0058 .dbline 78
0058 ; MCUCR = 0x00;
0058 2224 clr R2
005A 25BE out 0x35,R2
005C .dbline 79
005C ; GICR = 0x00;
005C 2BBE out 0x3b,R2
005E .dbline 80
005E ; TIMSK = 0x40; //timer interrupt sources
005E 80E4 ldi R24,64
0060 89BF out 0x39,R24
0062 .dbline 81
0062 ; SEI(); //re-enable interrupts
0062 7894 sei
0064 .dbline -2
0064 L5:
0064 .dbline 0 ; func end
0064 0895 ret
0066 .dbend
0066 .dbfunc e del _del fV
0066 ; time -> R16,R17
.even
0066 _del::
0066 .dbline -1
0066 .dbline 86
0066 ; }
0066 ;
0066 ; /* 微秒级延时程序 */
0066 ; void del(int time)
0066 ; {
0066 L7:
0066 .dbline 88
0066 ; do
0066 ; {
0066 .dbline 89
0066 ; time--;
0066 0150 subi R16,1
0068 1040 sbci R17,0
006A .dbline 90
006A ; }
006A L8:
006A .dbline 91
006A ; while (time>1);
006A 81E0 ldi R24,1
006C 90E0 ldi R25,0
006E 8017 cp R24,R16
0070 9107 cpc R25,R17
0072 CCF3 brlt L7
0074 .dbline -2
0074 L6:
0074 .dbline 0 ; func end
0074 0895 ret
0076 .dbsym r time 16 I
0076 .dbend
0076 .dbfunc e delay_1ms _delay_1ms fV
0076 ; i1 -> R16,R17
.even
0076 _delay_1ms::
0076 .dbline -1
0076 .dbline 96
0076 ; }
0076 ;
0076 ; /* 毫秒级延时程序 */
0076 ; void delay_1ms(void)
0076 ; { unsigned int i1;
0076 .dbline 97
0076 ; for(i1=1;i1<(unsigned int)(xtal*143-2);i1++)
0076 01E0 ldi R16,1
0078 10E0 ldi R17,0
007A 02C0 rjmp L14
007C L11:
007C .dbline 98
007C L12:
007C .dbline 97
007C 0F5F subi R16,255 ; offset = 1
007E 1F4F sbci R17,255
0080 L14:
0080 .dbline 97
0080 0637 cpi R16,118
0082 E4E0 ldi R30,4
0084 1E07 cpc R17,R30
0086 D0F3 brlo L11
0088 .dbline -2
0088 L10:
0088 .dbline 0 ; func end
0088 0895 ret
008A .dbsym r i1 16 i
008A .dbend
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