cpucache.inc

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var
  DescriptorsAr:array[0..15] of word;

function cCPUid.FillCacheInfo: boolean;
  var k:integer;
begin
  try
        flevel1.divided:=true;
        flevel1.icache.is_trace:=false;
        flevel2.is_l2_cache:=true;
        if (fCPUdata.extended[0].regEAX>=$80000005)
         and (not (fCPUdata.standart[0].regEAX>=2)) then
          begin
           {with extended info}
           {flevel 1:}
            flevel1.itlb.associativity_4k:=extract_dw(fCPUdata.extended[5].regEBX,8,15);
            flevel1.itlb.associativity_2m:=extract_dw(fCPUdata.extended[5].regEAX,8,15);
            flevel1.itlb.entries_4k:=extract_dw(fCPUdata.extended[5].regEBX,0,7);
            flevel1.itlb.entries_2m:=extract_dw(fCPUdata.extended[5].regEAX,0,7);
            flevel1.dtlb.associativity_4k:=extract_dw(fCPUdata.extended[5].regEBX,24,31);
            flevel1.dtlb.associativity_2m:=extract_dw(fCPUdata.extended[5].regEAX,24,31);
            flevel1.dtlb.entries_4k:=extract_dw(fCPUdata.extended[5].regEBX,16,23);
            flevel1.dtlb.entries_2m:=extract_dw(fCPUdata.extended[5].regEAX,16,23);
            flevel1.icache.size:=extract_dw(fCPUdata.extended[5].regEDX,24,31);
            flevel1.icache.associativity:=extract_dw(fCPUdata.extended[5].regEDX,16,23);
            flevel1.icache.linesize:=extract_dw(fCPUdata.extended[5].regEDX,0,7);
            flevel1.icache.linespertag:=extract_dw(fCPUdata.extended[5].regEDX,8,15);
            flevel1.dcache.size:=extract_dw(fCPUdata.extended[5].regECX,24,31);
            flevel1.dcache.associativity:=extract_dw(fCPUdata.extended[5].regECX,16,23);
            flevel1.dcache.linesize:=extract_dw(fCPUdata.extended[5].regECX,0,7);
            flevel1.dcache.linespertag:=extract_dw(fCPUdata.extended[5].regECX,8,15);
           {flevel 2:}
           if (fCPUdata.extended[0].regEAX>=$80000006) then
           begin 
            flevel2.itlb.entries_4k:=extract_dw(fCPUdata.extended[6].regEBX,0,11);
            flevel2.itlb.entries_2m:=extract_dw(fCPUdata.extended[6].regEAX,0,11);
            flevel2.dtlb.entries_4k:=extract_dw(fCPUdata.extended[6].regEBX,16,27);
            flevel2.dtlb.entries_2m:=extract_dw(fCPUdata.extended[6].regEAX,16,27);
            flevel2.cache.linesize:=extract_dw(fCPUdata.extended[6].regECX,0,7);
            case extract_dw(fCPUdata.extended[6].regEAX,28,31) of
              0: flevel2.dtlb.associativity_2m:=0;
              1: flevel2.dtlb.associativity_2m:=1;
              2: flevel2.dtlb.associativity_2m:=2;
              4: flevel2.dtlb.associativity_2m:=4;
              6: flevel2.dtlb.associativity_2m:=8;
              8: flevel2.dtlb.associativity_2m:=16;
             15: flevel2.dtlb.associativity_2m:=255;
            end;
            case extract_dw(fCPUdata.extended[6].regEAX,12,15) of
              0: flevel2.itlb.associativity_2m:=0;
              1: flevel2.itlb.associativity_2m:=1;
              2: flevel2.itlb.associativity_2m:=2;
              4: flevel2.itlb.associativity_2m:=4;
              6: flevel2.itlb.associativity_2m:=8;
              8: flevel2.itlb.associativity_2m:=16;
             15: flevel2.itlb.associativity_2m:=255;
            end;
            case extract_dw(fCPUdata.extended[6].regEBX,28,31) of
              0: flevel2.dtlb.associativity_4k:=0;
              1: flevel2.dtlb.associativity_4k:=1;
              2: flevel2.dtlb.associativity_4k:=2;
              4: flevel2.dtlb.associativity_4k:=4;
              6: flevel2.dtlb.associativity_4k:=8;
              8: flevel2.dtlb.associativity_4k:=16;
             15: flevel2.dtlb.associativity_4k:=255;
            end;
            case extract_dw(fCPUdata.extended[6].regEBX,12,15) of
              0: flevel2.itlb.associativity_4k:=0;
              1: flevel2.itlb.associativity_4k:=1;
              2: flevel2.itlb.associativity_4k:=2;
              4: flevel2.itlb.associativity_4k:=4;
              6: flevel2.itlb.associativity_4k:=8;
              8: flevel2.itlb.associativity_4k:=16;
             15: flevel2.itlb.associativity_4k:=255;
            end;
           {Other specific cases}
            if (fCPUid_m.std_vendor_string='CentaurHauls') and
                 (fCPUid_m.std_family=6) and
                   ((fCPUid_m.std_model=7) or (fCPUid_m.std_model=8))
                  then
                    begin
                     {VIA C3 0670h..068Fh:}
                     flevel2.cache.size:=extract_dw(fCPUdata.extended[6].regECX,24,31);
                     flevel2.cache.associativity:=extract_dw(fCPUdata.extended[6].regECX,16,23);
                     flevel2.cache.linespertag:=extract_dw(fCPUdata.extended[6].regECX,8,15);
                   end
                 else
                   begin
                    {Other:}
                    if ((fCPUid_m.std_vendor_string='AuthenticAMD') and
                       (fCPUid_m.std_family=6) and
                       (fCPUid_m.std_model=3) and
                       (fCPUid_m.std_stepping=0) and
                       (extract_dw(fCPUdata.extended[6].regECX,16,31)=1))
                     then
                       flevel2.cache.size:=64
                     else
                       flevel2.cache.size:=extract_dw(fCPUdata.extended[6].regECX,16,31);
            case extract_dw(fCPUdata.extended[6].regECX,12,15) of
              0: flevel2.cache.associativity:=0;
              1: flevel2.cache.associativity:=1;
              2: flevel2.cache.associativity:=2;
              4: flevel2.cache.associativity:=4;
              6: flevel2.cache.associativity:=8;
              8: flevel2.cache.associativity:=16;
             15: flevel2.cache.associativity:=255;
            end;
            if ((fCPUid_m.std_vendor_string='CentaurHauls') and
                 (fCPUid_m.std_family=6) and
                 (fCPUid_m.std_model=9) and
                (fCPUid_m.std_stepping=1) and
                (extract_dw(fCPUdata.extended[6].regECX,12,15)=0))
              then
                flevel2.cache.associativity:=16;
                flevel2.cache.linespertag:=extract_dw(fCPUdata.extended[6].regECX,8,11);
              end;
        end; // L2 if end
            {/with extended info}
        end
    else
  if (fCPUdata.standart[0].regEAX>=2) and
        (fCPUid_m.std_vendor_string='GenuineIntel') then
       begin
         {standart info only - using descriptors}
         DescriptorsAr[1]:=extract_dw(fCPUdata.standart[2].regEAX,8,15);
         DescriptorsAr[2]:=extract_dw(fCPUdata.standart[2].regEAX,16,23);
         DescriptorsAr[3]:=extract_dw(fCPUdata.standart[2].regEAX,24,31);
         DescriptorsAr[4]:=extract_dw(fCPUdata.standart[2].regEBX,0,7);
         DescriptorsAr[5]:=extract_dw(fCPUdata.standart[2].regEBX,8,15);
         DescriptorsAr[6]:=extract_dw(fCPUdata.standart[2].regEBX,16,23);
         DescriptorsAr[7]:=extract_dw(fCPUdata.standart[2].regEBX,24,31);
         DescriptorsAr[8]:=extract_dw(fCPUdata.standart[2].regECX,0,7);
         DescriptorsAr[9]:=extract_dw(fCPUdata.standart[2].regECX,8,15);
         DescriptorsAr[10]:=extract_dw(fCPUdata.standart[2].regECX,16,23);
         DescriptorsAr[11]:=extract_dw(fCPUdata.standart[2].regECX,24,31);
         DescriptorsAr[12]:=extract_dw(fCPUdata.standart[2].regEDX,0,7);
         DescriptorsAr[13]:=extract_dw(fCPUdata.standart[2].regEDX,8,15);
         DescriptorsAr[14]:=extract_dw(fCPUdata.standart[2].regEDX,16,23);
         DescriptorsAr[15]:=extract_dw(fCPUdata.standart[2].regEDX,24,31);
         for k:=1 to 15 do
           begin
             case DescriptorsAr[k] of
               $01:begin
                 flevel1.itlb.associativity_4k:=4;
                 flevel1.itlb.entries_4k:=32;
               end;
               $02:begin
                 flevel1.itlb.associativity_2m:=255;
                 flevel1.itlb.entries_2m:=2;
               end;
               $03:begin
                 flevel1.dtlb.associativity_4k:=4;
                 flevel1.dtlb.entries_4k:=64;
               end;
               $04:begin
                 flevel1.dtlb.associativity_2m:=4;
                 flevel1.dtlb.entries_2m:=8;
               end;
               $06:begin
                 flevel1.icache.size:=8;
                 flevel1.icache.associativity:=4;
                 flevel1.icache.linesize:=32;
               end;
               $08:begin
                 flevel1.icache.size:=16;
                 flevel1.icache.associativity:=4;
                 flevel1.icache.linesize:=32;
               end;
               $0A:begin
                 flevel1.dcache.size:=8;
                 flevel1.dcache.associativity:=2;
                 flevel1.dcache.linesize:=32;
               end;
               $0C:begin
                 flevel1.dcache.size:=16;
                 flevel1.dcache.associativity:=4;
                 flevel1.dcache.linesize:=32;
               end;
               $10:begin
                 flevel1.dcache.size:=16;
                 flevel1.dcache.associativity:=4;
                 flevel1.dcache.linesize:=32;
               end;
              $15:begin
                 flevel1.icache.size:=16;
                 flevel1.icache.associativity:=4;
                 flevel1.icache.linesize:=32;
              end;
              $1A:begin
                 flevel2.cache.size:=96;
                 flevel2.cache.associativity:=6;
                 flevel2.cache.linesize:=64;
              end;


    $22:  begin
          flevel3.is_l3_cache:=true;
          flevel3.cache.size:=512;
          flevel3.cache.associativity:=4;
          flevel3.cache.linesize:=64;
          flevel3.cache.sectors:=2;
          end;
    $23:  begin
          flevel3.is_l3_cache:=true;
          flevel3.cache.size:=1024;
          flevel3.cache.associativity:=8;
          flevel3.cache.linesize:=64;
          flevel3.cache.sectors:=2;
          end;
    $25:  begin
          flevel3.is_l3_cache:=true;
          flevel3.cache.size:=2048;
          flevel3.cache.associativity:=8;
          flevel3.cache.linesize:=64;
          flevel3.cache.sectors:=2;
          end;
    $29:  begin
          flevel3.is_l3_cache:=true;
          flevel3.cache.size:=4096;
          flevel3.cache.associativity:=8;
          flevel3.cache.linesize:=64;
          flevel3.cache.sectors:=2;
          end;
    $2C:  begin
          flevel1.dcache.size:=32;
          flevel1.dcache.associativity:=8;
          flevel1.dcache.linesize:=64;
          end;
    $30:  begin
          flevel1.icache.size:=32;
          flevel1.icache.associativity:=8;
          flevel1.icache.linesize:=64;
          end;
    $39:  begin
          flevel2.cache.size:=128;
          flevel2.cache.associativity:=4;
          flevel2.cache.linesize:=64;
          end;
    $3B:  begin
          flevel2.cache.size:=128;
          flevel2.cache.associativity:=2;
          flevel2.cache.linesize:=64;
          end;