par4chkd.c

基于PC104的24位数据采集器的完整源码

        dbg4_printk( "Par4ch_BdCtrlMode\n" );


        // Set the PAR4CH BdCtrlMode bits:
        //
        // These bits control the operating mode of the PAR4CH.  When
        // the mode is HALT_INIT, the PC has control of the sclk and sdi
        // pins on the ADS1210s.  All other modes are controlled by the
        // XCR5128.
        //

        Dev->BdCtrlValue &= ~(BDCTRL_MODE0 | BDCTRL_MODE1);
        Dev->BdCtrlValue |= (Value & (BDCTRL_MODE0 | BDCTRL_MODE1));

        Par4ch_BdCtrlWr( Dev, Dev->BdCtrlValue );

        return;


}
SRLOCAL void Par4ch_BdCtrlDsync( DEVINFO *Dev, unsigned char Value ) {

        dbg4_printk( "Par4ch_BdCtrlDsync\n" );


        // Set the BdCtrl (and ADS1210) Dsync pin high or low.

        Dev->BdCtrlValue &= ~BDCTRL_DSYNC;
        Dev->BdCtrlValue |= (Value & BDCTRL_DSYNC);

        Par4ch_BdCtrlWr( Dev, Dev->BdCtrlValue);

}
SRLOCAL void Par4ch_BdCtrlFifoReset( DEVINFO *Dev, unsigned char Value ) {

        dbg4_printk( "Par4ch_BdCtrlFifoReset\n" );


        // Set the BdCtrl Fifo Reset bit high or low.
        //
        // When the Fifo Reset bit is high, all addresses are held
        // at zero.  Low and the Fifo operates normally.
        //
        //

        Dev->BdCtrlValue &= ~BDCTRL_FIFORESET;
        Dev->BdCtrlValue |= (Value & BDCTRL_FIFORESET);

        Par4ch_BdCtrlWr( Dev, Dev->BdCtrlValue );
        
        return;

}
SRLOCAL void Par4ch_BdCtrlUserLed( DEVINFO *Dev, int State ) {

        dbg4_printk( "Par4ch_BdCtrlUserLed\n" );


        // Set the BdCtrl User Led bit on or off.

        Dev->BdCtrlValue &= ~BDCTRL_USERLED;

        if ( State )

                Dev->BdCtrlValue |= BDCTRL_USERLED_ON;
        else
                Dev->BdCtrlValue |= BDCTRL_USERLED_OFF;


        Par4ch_BdCtrlWr( Dev, Dev->BdCtrlValue );
        
        return;

}







/* ADS1210 instruction register bit assignments:

These defines give the bit assigments and values of the internal
ADS1210 registers.  They are used in the ADS1210_xxx functions below.

*/

#define ADS1210_WRITE                   (0x00 << 7)
#define ADS1210_READ                    (0x01 << 7)

#define ADS1210_NBYTES_1                (0x00 << 5)
#define ADS1210_NBYTES_2                (0x01 << 5)
#define ADS1210_NBYTES_3                (0x02 << 5)
#define ADS1210_NBYTES_4                (0x03 << 5)

#define ADS1210_ADDR_DATA               (0x00 << 0)
#define ADS1210_ADDR_CONTROL            (0x04 << 0)
#define ADS1210_ADDR_OFFSET             (0x08 << 0)
#define ADS1210_ADDR_FSCAL              (0x0C << 0)


// ADS1210 command register bit assignments:

#define ADS1210_BIAS_GEN_OFF            (0x0L << 31)
#define ADS1210_BIAS_GEN_ON             (0x1L << 31)

#define ADS1210_INT_REF_OFF             (0x0L << 30)
#define ADS1210_INT_REF_ON              (0x1L << 30)

#define ADS1210_DATA_FORMAT_SIGNED      (0x0L << 29)
#define ADS1210_DATA_FORMAT_OFFSET      (0x1L << 29)

#define ADS1210_DATA_FORMAT( VALUE )    ( ((unsigned long)VALUE & 0x1L) << 29 )

#define ADS1210_BIPOLAR                 (0x0L << 28)
#define ADS1210_UNIPOLAR                (0x1L << 28)

#define ADS1210_BYTE_DESCEND            (0x0L << 27)
#define ADS1210_BYTE_ASCEND             (0x1L << 27)

#define ADS1210_MSB_FIRST               (0x0L << 26)
#define ADS1210_MSB_LAST                (0x1L << 26)

#define ADS1210_SDO_DISABLED            (0x0L << 25)
#define ADS1210_SDO_ENABLED             (0x1L << 25)

#define ADS1210_DRDY                    (0x1L << 24)  // << read  only
#define ADS1210_DSYNC_NOCHANGE          (0x0L << 24)  // << write only
#define ADS1210_DSYNC_ASSERT            (0x1L << 24)  // << write only

#define ADS1210_CAL_MODE_NORMAL         (0x0L << 21)
#define ADS1210_CAL_MODE_SELF           (0x1L << 21)
#define ADS1210_CAL_MODE_SYS_OFF        (0x2L << 21)
#define ADS1210_CAL_MODE_SYS_FULL       (0x3L << 21)
#define ADS1210_CAL_MODE_SYS_PSEUDO     (0x4L << 21)
#define ADS1210_CAL_MODE_BACK           (0x5L << 21)
#define ADS1210_CAL_MODE_SLEEP          (0x6L << 21)

#define ADS1210_CAL_MODE( VALUE )       ( ((unsigned long)VALUE & 0x7L) << 21 )

#define ADS1210_GAIN_1                  (0x0L << 18)
#define ADS1210_GAIN_2                  (0x1L << 18)
#define ADS1210_GAIN_4                  (0x2L << 18)
#define ADS1210_GAIN_8                  (0x3L << 18)
#define ADS1210_GAIN_16                 (0x4L << 18)

#define ADS1210_GAIN( VALUE )           ( ((unsigned long)VALUE & 0x7L) << 18 )

#define ADS1210_CHAN_SELECT_0           (0x0L << 16)

#define ADS1210_TURBO_1                 (0x0L << 13)
#define ADS1210_TURBO_2                 (0x1L << 13)
#define ADS1210_TURBO_4                 (0x2L << 13)
#define ADS1210_TURBO_8                 (0x3L << 13)
#define ADS1210_TURBO_16                (0x4L << 13)

#define ADS1210_TURBO( VALUE )          ( ((unsigned long)VALUE & 0x7L) << 13 )
#define ADS1210_DECIMATION( VALUE )     (((unsigned long)VALUE & 0x1FFFL) << 0)






/* ADS1210 SCLK, SDI READ/WRITE BYTE PIN FUNCTIONS:

These helper functions twiddle the ADS1210 sclk, and sdi pins via the
BdCtrl register to read and write single bytes from the ADS1210.

They are designed to be used when the BDCTRL_RUN bit is off.  When the
run bit is on the XCR5128 has control of the A/D converters.

*/

SRLOCAL void Par4ch_ADS1210_WriteByte( DEVINFO *Dev, unsigned char Value ) {

        unsigned char CtrlReg;
        int Bit;
        

        dbg4_printk( "Par4ch_ADS1210_WriteByte\n" );

        CtrlReg  = Dev->BdCtrlValue;


        // Write a byte to the ADS1210 via the PAR4CH BdCtrl register.
        //
        // A single byte is written MSB first, a bit at a time.  Since
        // the sdi pin is in parallel on all the converters, the same
        // byte is written to each channel.
        //
        // See the ADS1210 spec sheet for the sclk, sdi timing on write
        // operations.
        //

        for ( Bit = 0x80 ; Bit > 0 ; Bit >>= 1 ) {


                // Drive sclk high and assert the data bit.

                CtrlReg |= BDCTRL_SCLK;

                if ( Value & Bit )

                        CtrlReg |= BDCTRL_SDI;
                else
                        CtrlReg &= ~BDCTRL_SDI;

                Par4ch_BdCtrlWr( Dev, CtrlReg );



                // Drive sclk low to latch it into the ADS1210.

                CtrlReg &= ~BDCTRL_SCLK;

                Par4ch_BdCtrlWr( Dev, CtrlReg );

                }

        Dev->BdCtrlValue = CtrlReg;

        return;

}
SRLOCAL void Par4ch_ADS1210_ReadByte( DEVINFO *Dev, unsigned char *Value ) {

        unsigned char CtrlReg, PortValue;
        int Bit;

        
        dbg4_printk( "Par4ch_ADS1210_ReadByte\n" );

        CtrlReg = Dev->BdCtrlValue;


        // Read a byte from the ADS1210 via the PAR4CH BdCtrl register.
        //
        // When the BDCTRL_RUN bit is off, the sdo pins from each
        // converter are mapped into the low nibble of EPP AsRd.
        //
        // See the ADS1210 spec sheet for the sclk, sdo timing on read
        // operations.
        //


        *Value = 0;

        for ( Bit = 0x80 ; Bit > 0 ; Bit >>= 1 ) {

                // Toggle the ADS1210 sclk high.

                CtrlReg |= BDCTRL_SCLK;

                Par4ch_BdCtrlWr( Dev, CtrlReg );



                // Read the bit.

                Dev->ParPortAsRd( Dev, &PortValue );



                // TEMPORARILY JUST READ BACK A/D ON CHANNEL 0.
                //
                // WHY NOT EXPAND TO GET BACK ALL 4 CHANNELS ????
                // WHY NOT EXPAND TO GET BACK ALL 4 CHANNELS ????
                // WHY NOT EXPAND TO GET BACK ALL 4 CHANNELS ????
                //

                if ( PortValue & 0x01 )

                        *Value |= Bit;
                else
                        *Value &= ~Bit;


                // Toggle the ADS1210 sclk low for next cycle.

                CtrlReg &= ~BDCTRL_SCLK;

                Par4ch_BdCtrlWr( Dev, CtrlReg );


                }

        Dev->BdCtrlValue = CtrlReg;

        return;
}





/* ADS1210 INTERNAL REGISTER READ and WRITE:

These functions read and write the ADS1210 internal registers.

They should be used only when the board is not executing and the
BdCtrl RUN bit is off.  Calling them while the ADS1210s are executing
will corrupt board operation.

See the Burr Brown spec sheet for details on the ADS1210 register bit
assigments.

*/

SRLOCAL void Par4ch_ADS1210_ReadReg24( DEVINFO *Dev, int Reg, long *Value ) {
        
        unsigned char Inst;

        dbg4_printk( "Par4ch_ADS1210_ReadReg24\n" );


        // Read an ADS1210 24 bit register.


        Inst = ADS1210_READ | ADS1210_NBYTES_3 | Reg;

        Par4ch_ADS1210_WriteByte( Dev, Inst );

            *( (char *)Value + 3 ) = 0;

                Par4ch_ADS1210_ReadByte( Dev, (char *)Value + 2);
                Par4ch_ADS1210_ReadByte( Dev, (char *)Value + 1);
                Par4ch_ADS1210_ReadByte( Dev, (char *)Value + 0);

}
SRLOCAL void Par4ch_ADS1210_ReadReg32( DEVINFO *Dev, int Reg, long *Value ) {
        
        unsigned char Inst;

        dbg4_printk( "Par4ch_ADS1210_ReadReg32\n" );

        // Read an ADS1210 32 bit register.

        Inst = ADS1210_READ | ADS1210_NBYTES_4 | Reg ;

        Par4ch_ADS1210_WriteByte( Dev, Inst );

                Par4ch_ADS1210_ReadByte( Dev, (char *)Value + 3);
                Par4ch_ADS1210_ReadByte( Dev, (char *)Value + 2);
                Par4ch_ADS1210_ReadByte( Dev, (char *)Value + 1);
                Par4ch_ADS1210_ReadByte( Dev, (char *)Value + 0);

}
SRLOCAL void Par4ch_ADS1210_WriteReg24( DEVINFO *Dev, int Reg, unsigned long Value ) {

        unsigned char Inst;
        
        dbg4_printk( "Par4ch_ADS1210_WriteReg24\n" );


        // Write to an ADS1210 24 bit register.

        Inst = ADS1210_WRITE | ADS1210_NBYTES_3 | Reg;

        Par4ch_ADS1210_WriteByte( Dev, Inst );

                Par4ch_ADS1210_WriteByte(Dev,((char *)&Value)[2]);
                Par4ch_ADS1210_WriteByte(Dev,((char *)&Value)[1]);
                Par4ch_ADS1210_WriteByte(Dev,((char *)&Value)[0]);

}
SRLOCAL void Par4ch_ADS1210_WriteReg32( DEVINFO *Dev, int Reg, unsigned long Value ) {

        unsigned char Inst;
        
        dbg4_printk( "Par4ch_ADS1210_WriteReg32\n" );


        // Write to an ADS1210 32 bit register.

        Inst = ADS1210_WRITE | ADS1210_NBYTES_4 | Reg;

        Par4ch_ADS1210_WriteByte( Dev, Inst );

                Par4ch_ADS1210_WriteByte(Dev,((char *)&Value)[3]);
                Par4ch_ADS1210_WriteByte(Dev,((char *)&Value)[2]);
                Par4ch_ADS1210_WriteByte(Dev,((char *)&Value)[1]);
                Par4ch_ADS1210_WriteByte(Dev,((char *)&Value)[0]);
}








/* BASIC DRAM FIFO FUNCTIONS:

These helper functions communicate with the PAR4CH DRAM FIFO.

*/

SRLOCAL void Par4ch_DramFifoReset( DEVINFO *Dev ) {

        // Reset the DRAM FIFO read and write addresses and sanity bit:
        //
        // The BdCtrl run bit should be off and ADS1210 drdy deasserted.
        //

        Par4ch_BdCtrlFifoReset( Dev, BDCTRL_FIFORESET_HIGH );
        Par4ch_BdCtrlFifoReset( Dev, BDCTRL_FIFORESET_LOW );

        Dev->ExpectedFifoSanity = 0x00;
        
}
SRLOCAL void Par4ch_DramFifoRd( DEVINFO *Dev, unsigned char *Value ) {

        dbg4_printk( "Par4ch_DramFifoRd\n" );


        // Read a single nibble (packed in a byte) from the DRAM FIFO.

        Dev->ParPortDsRd( Dev, Value );

        *Value &= 0x0F;


}
SRLOCAL void Par4ch_DramFifoWr( DEVINFO *Dev, unsigned char Value ) {

        dbg4_printk( "Par4ch_DramFifoWr\n" );

        
        // Write a single nibble (packed in a byte) to the DRAM FIFO.
        //
        // This function only works if the BdCtrlRun bit is off.  If
        // BdCtrlRun is on, the DRAM is connected to the A/D converters,