epl_shift_register.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

---- Data: 2004,8,4;

---- // EPL_Shift_Register;
---- // 3 bits Shift Register: Early_Code, Prompt_Code,Late_Code;
----    Generate the output of Prompt and Tracking;
---- // Reset  : active low level ;
---- // SelOfEL: slect the Early_Code and Late_Code;
---- // The order of Shift Register : Early_Code => Prompt_Code => Late_Code; 


---- Questions:
---- 1) the output ??? when Reset;
---- 2) 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity EPL_Shift_Register is
    Port ( CodeClk2    : in std_logic;
           Reset       : in std_logic;
           SelOfEL     : in std_logic;
           CA_Code     : in std_logic;
           CA_Prompt   : out std_logic;
           CA_Tracking : out std_logic);
end EPL_Shift_Register;

architecture rtl of EPL_Shift_Register is

   signal Late_Code, Prompt_Code, Early_Code : std_logic;

begin

   process(CodeClk2,Reset)
   begin
      if Reset='0' then
	    Late_Code   <= '0';
	    Prompt_Code <= '0';
	    Early_Code  <= '0';	    
	 elsif CodeClk2'event and CodeClk2='1' then
	    Early_Code  <= CA_Code;					  --这是三条并行语句，不是顺序语句
	    Prompt_Code <= Early_Code;				  --此处的Early_Code是上一次的CA_Code的值
	    Late_Code   <= Prompt_Code;
      end if;
   end process;

     CA_Prompt   <= Prompt_Code;
     CA_Tracking <= Late_Code when SelOfEL = '1' else
                  Early_Code;


end rtl;