slew_ofgenerator_tb.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

-- VHDL Test Bench Created from source file slewof_generate.vhd -- 09:16:57 09/21/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT slewof_generate
	PORT(
		sampleclk : IN std_logic;
		codeclk2 : IN std_logic;
		rstb : IN std_logic;
		code_end : IN std_logic;
		codeofslew : IN std_logic_vector(10 downto 0);          
		countoftemp : OUT std_logic_vector(10 downto 0);
		slewofcount : OUT std_logic_vector(10 downto 0);
		slew : OUT std_logic
		);
	END COMPONENT;

	SIGNAL sampleclk :  std_logic;
	SIGNAL codeclk2 :  std_logic;
	SIGNAL rstb :  std_logic;
	SIGNAL code_end :  std_logic;
	SIGNAL codeofslew :  std_logic_vector(10 downto 0);
	SIGNAL countoftemp :  std_logic_vector(10 downto 0);
	SIGNAL slewofcount :  std_logic_vector(10 downto 0);
	SIGNAL slew :  std_logic;
	signal count : integer range 0 to 2045 ;

BEGIN

	uut: slewof_generate PORT MAP(
		sampleclk => sampleclk,
		codeclk2 => codeclk2,
		rstb => rstb,
		code_end => code_end,
		codeofslew => codeofslew,
		countoftemp => countoftemp,
		slewofcount => slewofcount,
		slew => slew
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
	 sampleclk <= '1' ;
	 wait for 200 ns;
	 sampleclk <= '0';
	 wait for 200 ns;
	 end process;

	 process
	  begin
	    codeclk2 <= '1' ;
		 wait for 400 ns;
		 codeclk2 <= '0' ;
		 wait for 400 ns;
		 end process;
generater_rstb: process
                  begin
						 rstb <= '0';
						 wait for 1000 ns;
						 rstb <= '1';
						 wait;
						 end process;
generator_code_end : process(codeclk2)
                        begin
								  if codeclk2 'event and codeclk2 ='1' then
								       count <= count + 1 ;
										   if count = 2045 then 
											    code_end <= '1' ;
												  count <= 0;
                                  end if;
                            end if;
                       end process;
codeofslew_generator: process
                        begin
								  codeofslew <= "00001111000";
								  wait for 100000 ns;
								  codeofslew <= "00000000111";
								  

      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;