debug_detect_peakvalue_timesim.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

  signal resultoftemp_2_FFX_RST : STD_LOGIC; 
  signal resultoftemp_2_FFY_RST : STD_LOGIC; 
  signal flagofdetect_33_FFY_RST : STD_LOGIC; 
  signal resultoftemp_0_FFX_RST : STD_LOGIC; 
  signal resultoftemp_0_FFY_RST : STD_LOGIC; 
  signal resultoftemp_14_FFY_RST : STD_LOGIC; 
  signal countofcompute_1_FFX_RST : STD_LOGIC; 
  signal flagofgetcodeslew_FFY_RST : STD_LOGIC; 
  signal countofcompute_1_FFY_RST : STD_LOGIC; 
  signal countofcompute_2_FFY_RST : STD_LOGIC; 
  signal resultoftemp_12_FFX_RST : STD_LOGIC; 
  signal resultoftemp_8_FFX_RST : STD_LOGIC; 
  signal resultoftemp_6_FFY_RST : STD_LOGIC; 
  signal resultoftemp_8_FFY_RST : STD_LOGIC; 
  signal resultoftemp_6_FFX_RST : STD_LOGIC; 
  signal resultoftemp_10_FFX_RST : STD_LOGIC; 
  signal resultoftemp_12_FFY_RST : STD_LOGIC; 
  signal resultoftemp_4_FFX_RST : STD_LOGIC; 
  signal resultoftemp_4_FFY_RST : STD_LOGIC; 
  signal resultoftemp_14_FFX_RST : STD_LOGIC; 
  signal resultoftemp_16_FFY_RST : STD_LOGIC; 
  signal resultoftemp_16_FFX_RST : STD_LOGIC; 
  signal resultoftemp_18_FFY_RST : STD_LOGIC; 
  signal resultoftemp_18_FFX_RST : STD_LOGIC; 
  signal resultoftemp_20_FFY_RST : STD_LOGIC; 
  signal resultoftemp_20_FFX_RST : STD_LOGIC; 
  signal resultoftemp_22_FFY_RST : STD_LOGIC; 
  signal resultoftemp_32_FFX_RST : STD_LOGIC; 
  signal CodeOfSlew_0_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal resultoftemp_26_FFY_RST : STD_LOGIC; 
  signal resultoftemp_26_FFX_RST : STD_LOGIC; 
  signal resultoftemp_28_FFY_RST : STD_LOGIC; 
  signal resultoftemp_28_FFX_RST : STD_LOGIC; 
  signal resultoftemp_30_FFY_RST : STD_LOGIC; 
  signal resultoftemp_30_FFX_RST : STD_LOGIC; 
  signal CodeOfSlew_0_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_0_OUTPUT_OFF_OCEINV : STD_LOGIC; 
  signal CodeOfSlew_0_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal CodeOfSlew_4_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_10_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_3_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_5_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_6_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_7_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_8_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_9_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_1_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal CodeOfSlew_2_OUTPUT_OFF_O1INVNOT : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal resultoftemp : STD_LOGIC_VECTOR ( 32 downto 0 ); 
  signal flagofdetect_1 : STD_LOGIC_VECTOR ( 33 downto 33 ); 
  signal flagofdetect : STD_LOGIC_VECTOR ( 33 downto 33 ); 
  signal qp_square : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal ip_square : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal Sum_I_Prompt_c : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Sum_Q_Prompt_c : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal countofcompute : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal temp_codeofslew : STD_LOGIC_VECTOR ( 0 downto 0 ); 
begin
  GLOBAL_LOGIC0_ZERO : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  flagofdetect_1_cry_7_O_CYSELG_0 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => resultoftemp_7_rt,
      O => flagofdetect_1_cry_7_O_CYSELG
    );
  flagofdetect_1_cry_7_O_CYMUXG2_1 : X_MUX2
    port map (
      IA => flagofdetect_1_cry_7_O_LOGIC_ZERO,
      IB => flagofdetect_1_cry_7_O_CYMUXF2,
      SEL => flagofdetect_1_cry_7_O_CYSELG,
      O => flagofdetect_1_cry_7_O_CYMUXG2
    );
  flagofdetect_1_cry_7_O_CYMUXFAST_2 : X_MUX2
    port map (
      IA => flagofdetect_1_cry_7_O_CYMUXG2,
      IB => flagofdetect_1_cry_7_O_FASTCARRY,
      SEL => flagofdetect_1_cry_7_O_CYAND,
      O => flagofdetect_1_cry_7_O_CYMUXFAST
    );
  flagofdetect_1_cry_7_O_CYAND_3 : X_AND2
    port map (
      I0 => flagofdetect_1_cry_7_O_CYSELG,
      I1 => flagofdetect_1_cry_7_O_CYSELF,
      O => flagofdetect_1_cry_7_O_CYAND
    );
  flagofdetect_1_cry_7_O_FASTCARRY_4 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => flagofdetect_1_cry_5_O,
      O => flagofdetect_1_cry_7_O_FASTCARRY
    );
  flagofdetect_1_cry_7_O_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => flagofdetect_1_cry_7_O_CYMUXFAST,
      O => flagofdetect_1_cry_7_O
    );
  flagofdetect_1_cry_7_O_CYSELF_5 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => resultoftemp_6_rt,
      O => flagofdetect_1_cry_7_O_CYSELF
    );
  flagofdetect_1_cry_7_O_CYMUXF2_6 : X_MUX2
    port map (
      IA => flagofdetect_1_cry_7_O_LOGIC_ZERO,
      IB => flagofdetect_1_cry_7_O_LOGIC_ZERO,
      SEL => flagofdetect_1_cry_7_O_CYSELF,
      O => flagofdetect_1_cry_7_O_CYMUXF2
    );
  flagofdetect_1_cry_7_O_LOGIC_ZERO_7 : X_ZERO
    port map (
      O => flagofdetect_1_cry_7_O_LOGIC_ZERO
    );
  flagofdetect_1_cry_9_O_CYSELG_8 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => resultoftemp_9_rt,
      O => flagofdetect_1_cry_9_O_CYSELG
    );
  flagofdetect_1_cry_9_O_CYMUXG2_9 : X_MUX2
    port map (
      IA => flagofdetect_1_cry_9_O_LOGIC_ZERO,
      IB => flagofdetect_1_cry_9_O_CYMUXF2,
      SEL => flagofdetect_1_cry_9_O_CYSELG,
      O => flagofdetect_1_cry_9_O_CYMUXG2
    );
  flagofdetect_1_cry_9_O_CYMUXFAST_10 : X_MUX2
    port map (
      IA => flagofdetect_1_cry_9_O_CYMUXG2,
      IB => flagofdetect_1_cry_9_O_FASTCARRY,
      SEL => flagofdetect_1_cry_9_O_CYAND,
      O => flagofdetect_1_cry_9_O_CYMUXFAST
    );
  flagofdetect_1_cry_9_O_CYAND_11 : X_AND2
    port map (
      I0 => flagofdetect_1_cry_9_O_CYSELG,
      I1 => flagofdetect_1_cry_9_O_CYSELF,
      O => flagofdetect_1_cry_9_O_CYAND
    );
  flagofdetect_1_cry_9_O_FASTCARRY_12 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => flagofdetect_1_cry_7_O,
      O => flagofdetect_1_cry_9_O_FASTCARRY
    );
  flagofdetect_1_cry_9_O_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => flagofdetect_1_cry_9_O_CYMUXFAST,
      O => flagofdetect_1_cry_9_O
    );
  flagofdetect_1_cry_9_O_CYSELF_13 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => resultoftemp_8_rt,
      O => flagofdetect_1_cry_9_O_CYSELF
    );
  flagofdetect_1_cry_9_O_CYMUXF2_14 : X_MUX2
    port map (
      IA => flagofdetect_1_cry_9_O_LOGIC_ZERO,
      IB => flagofdetect_1_cry_9_O_LOGIC_ZERO,
      SEL => flagofdetect_1_cry_9_O_CYSELF,
      O => flagofdetect_1_cry_9_O_CYMUXF2
    );
  flagofdetect_1_cry_9_O_LOGIC_ZERO_15 : X_ZERO
    port map (
      O => flagofdetect_1_cry_9_O_LOGIC_ZERO
    );
  resultoftemp_10_CLKINV_16 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SampleClk_c,
      O => resultoftemp_10_CLKINV
    );
  resultoftemp_10_CYSELG_17 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => un7_resultoftemp_axb_11,
      O => resultoftemp_10_CYSELG
    );
  resultoftemp_10_CY0G_18 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => qp_square(11),
      O => resultoftemp_10_CY0G
    );
  resultoftemp_10_CYMUXG2_19 : X_MUX2
    port map (
      IA => resultoftemp_10_CY0G,
      IB => resultoftemp_10_CYMUXF2,
      SEL => resultoftemp_10_CYSELG,
      O => resultoftemp_10_CYMUXG2
    );
  resultoftemp_10_CYMUXFAST_20 : X_MUX2
    port map (
      IA => resultoftemp_10_CYMUXG2,
      IB => resultoftemp_10_FASTCARRY,
      SEL => resultoftemp_10_CYAND,
      O => resultoftemp_10_CYMUXFAST
    );
  resultoftemp_10_CYAND_21 : X_AND2
    port map (
      I0 => resultoftemp_10_CYSELG,
      I1 => resultoftemp_10_CYSELF,
      O => resultoftemp_10_CYAND
    );
  resultoftemp_10_FASTCARRY_22 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => un7_resultoftemp_cry_9_O,
      O => resultoftemp_10_FASTCARRY
    );
  resultoftemp_10_COUTUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => resultoftemp_10_CYMUXFAST,
      O => un7_resultoftemp_cry_11_O
    );
  resultoftemp_10_XORG_23 : X_XOR2
    port map (
      I0 => un7_resultoftemp_cry_10_O,
      I1 => un7_resultoftemp_axb_11,
      O => resultoftemp_10_XORG
    );
  resultoftemp_10_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => resultoftemp_10_XORG,
      O => un7_resultoftemp_s_11_n
    );
  resultoftemp_10_DYMUX_24 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => un7_resultoftemp_s_11_n,
      O => resultoftemp_10_DYMUX
    );
  resultoftemp_10_CYSELF_25 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => un7_resultoftemp_axb_10,
      O => resultoftemp_10_CYSELF
    );
  resultoftemp_10_CY0F_26 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => qp_square(10),
      O => resultoftemp_10_CY0F
    );
  resultoftemp_10_CYINIT_27 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => un7_resultoftemp_cry_9_O,
      O => resultoftemp_10_CYINIT
    );
  resultoftemp_10_CYMUXF : X_MUX2
    port map (
      IA => resultoftemp_10_CY0F,
      IB => resultoftemp_10_CYINIT,
      SEL => resultoftemp_10_CYSELF,
      O => un7_resultoftemp_cry_10_O
    );
  resultoftemp_10_CYMUXF2_28 : X_MUX2
    port map (
      IA => resultoftemp_10_CY0F,
      IB => resultoftemp_10_CY0F,
      SEL => resultoftemp_10_CYSELF,
      O => resultoftemp_10_CYMUXF2
    );
  resultoftemp_10_XORF_29 : X_XOR2
    port map (
      I0 => resultoftemp_10_CYINIT,
      I1 => un7_resultoftemp_axb_10,
      O => resultoftemp_10_XORF
    );
  resultoftemp_10_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => resultoftemp_10_XORF,
      O => un7_resultoftemp_s_10_n
    );
  resultoftemp_10_DXMUX_30 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => un7_resultoftemp_s_10_n,
      O => resultoftemp_10_DXMUX
    );
  resultoftemp_12_CLKINV_31 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => SampleClk_c,
      O => resultoftemp_12_CLKINV
    );
  resultoftemp_12_CYSELG_32 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => un7_resultoftemp_axb_13,
      O => resultoftemp_12_CYSELG
    );
  resultoftemp_12_CY0G_33 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => qp_square(13),
      O => resultoftemp_12_CY0G
    );
  resultoftemp_12_CYMUXG2_34 : X_MUX2
    port map (
      IA => resultoftemp_12_CY0G,
      IB => resultoftemp_12_CYMUXF2,
      SEL => resultoftemp_12_CYSELG,
      O => resultoftemp_12_CYMUXG2
    );
  resultoftemp_12_CYMUXFAST_35 : X_MUX2
    port map (
      IA => resultoftemp_12_CYMUXG2,
      IB => resultoftemp_12_FASTCARRY,
      SEL => resultoftemp_12_CYAND,
      O => resultoftemp_12_CYMUXFAST
    );
  resultoftemp_12_CYAND_36 : X_AND2
    port map (
      I0 => resultoftemp_12_CYSELG,
      I1 => resultoftemp_12_CYSELF,
      O => resultoftemp_12_CYAND
    );
  resultoftemp_12_FASTCARRY_37 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => un7_resultoftemp_cry_11_O,
      O => resultoftemp_12_FASTCARRY