slewof_generate.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

---- Data: 2004,8,5;

---- // Generate the Slew of Code_Slew ;
---- // Two cases:
----    1) Generate Slew by RSTB;
----    2) Generate Slew by Code_End;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity SlewOf_Generate is
    Port ( SampleClk  : in std_logic;
           CodeClk2   : in std_logic;
		 RSTB       : in std_logic;
           Code_End   : in std_logic;
		 CodeOfSlew : in std_logic_vector( 10 downto 0);
		 CountOfTemp: out std_logic_vector( 10 downto 0);
		 SlewOfCount: out std_logic_vector( 10 downto 0);
           Slew       : out std_logic
		 );
end SlewOf_Generate;

architecture rtl of SlewOf_Generate is

   signal RSTB_Delay,Code_Slew_EnWP,Code_Slew_WP,FlagOfEnable
						            : std_logic;
   signal NumOfSlew                       : integer range 0 to 2045;
   signal Count1,Count2,CountTemp,Count   : integer range 0 to 2045;

begin

   Generate_WritePluse_RSTB : process(SampleClk)
   begin
      if SampleClk'event and SampleClk='1' then
	    RSTB_Delay <= RSTB;
      end if;
   end process;
   Code_Slew_EnWP <= not RSTB_Delay;
   Code_Slew_WP   <= RSTB and Code_Slew_EnWP;


   NumOfSlew <= Conv_integer(CodeOfSlew);
   process(Code_Slew_WP)
   begin
      if Code_Slew_WP'event and Code_Slew_WP='1' then
	    if  Code_Slew_EnWP='1' then 
	    	   Count1 <= NumOfSlew;
         end if;
      end if;
   end process;

----   process(CodeClk2)
   process(Code_End)
   begin
      if Code_End'event and Code_End='1' then
	    Count2 <= NumOfSlew;
      end if;
	     
----      if CodeClk2'event and CodeClk2='1' then 
----	    if  Code_End='1' then 
----	        Count2 <= NumOfSlew;
----         end if;
----      end if;
   end process;

   process(CodeClk2,RSTB)
   begin
      if RSTB='0' then 
	    FlagOfEnable <='0';
	 elsif CodeClk2'event and Codeclk2='1' then 
	    FlagOfEnable <='1';
	 end if;
   end process;    

   CountTemp   <= Count1 when FlagOfEnable='0' else
                  Count2;
   CountOfTemp <= CONV_STD_LOGIC_VECTOR (CountTemp,11);

   CountOfCodeSlew : process(CodeClk2)
   begin
      if CodeClk2'event and CodeClk2='1' then
	    if  FlagOfEnable='0'or Code_End='1' then
	        Count <= CountTemp;
         elsif  Count= 0 then	   ----- Count=0 should not be revised, note that the case of CountTemp=0;
	        Count <= 0;
         else
	        Count <= Count-1;
         end if;
      end if;
   end process;
   SlewOfCount <= CONV_STD_LOGIC_VECTOR (Count,11);

   GenerateSlew : process(CodeClk2)
   begin
      if CodeClk2'event and CodeClk2='1' then
	    if FlagOfEnable='0'or Code_End='1' then
	       if  CountTemp=0 then		 ------ Add the condition;
	           Slew <= '1';
            else
		      Slew <= '0';
            end if;
	    elsif Count=1 then		 ----- when Count=1, Slew set high level;
	       Slew <= '1';
	    end if;
	 end if; 
   end process;


end rtl;