carry_dco.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

---- Simulation is right;

---- Date: 2004,8,8;
---- //// Carry_Dco;
---- //// The importan parameter:
---- //// 1) the Frequency of Carrier : 
----         88.54/63 = 1.4053968253968253968253968253968;
---- //// 2) the SampleClk : 
----         40/7     = 5.7142857142857142857142857142857;
---- //// 3) the standard Frequency Word : 
----         ((88.54/63)/(40/7))*(2^26)=16505052.27377777777777777777777;
----   ====>>> "00111110111101100011011100";

--     ====>>> "00111110101101010010000100";	  ------	  1399721.826Hz;


---- //// The map relation:
----  00 ==>> -1; 01 ==>> -2; 10 ==>> 1; 11 ==>> 2;
----  Cos :   2  1 -1 -2 -2 -1  1  2;
----  Sin :   1  2  2  1 -1 -2 -2 -1;
----		 ACC	   Cos	 Sin
----  0 => 000 =>  11  =>  10;
----  1 => 001 =>  10  =>  11;
----  2 => 010 =>  00  =>  11;
----  3 => 011 =>  01  =>  10;
----  4 => 100 =>  01  =>  00;
----  5 => 101 =>  00  =>  01;
----  6 => 110 =>  10  =>  01;
----	 7 => 111	=>  11  =>  00;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Carry_Dco is
    Port ( SampleClk : in  std_logic;
           Reset     : in  std_logic;
           Carry_Fre : in  std_logic_vector(25 downto 0);
           Enable    : in  std_logic;
           ValueOfCos: out std_logic_vector( 1 downto 0);
           ValueOfSin: out std_logic_vector( 1 downto 0)
		 );
end Carry_Dco;

architecture rtl of Carry_Dco is

   signal  ACC  :  std_logic_vector( 25 downto 0);
   signal  FW   :  std_logic_vector( 25 downto 0);
   signal  CosOfTemp : std_logic_vector( 1 downto 0);
   signal  SinOfTemp : std_logic_vector( 1 downto 0);

begin

  process(SampleClk,Reset)
  begin
     if Reset='0' then
----//// when simulate the output amplititude of Carry_Dco,
----//// use the "00100000000000000000000000";
-----------        FW <= "00100000000000000000000000";
----//////////////////////////////////////////////////----	    
	  -----    FW <= "00111110111101100011011100";  ------	1.4053MHz;
	       FW <= "00111110101101010010000100";	      ---	1.399721826MHz;
	  elsif SampleClk'event and SampleClk='1' then
	      if Enable='1' then
	         FW <= FW + Carry_Fre;
           end if;
     end if;
  end process;
  
  process (SampleClk,Reset)
  begin
     if Reset='0' then
	     ACC <= (others=>'0');
	elsif SampleClk'event and SampleClk='1' then
	       ACC <= ACC + FW;
     end if;
  end process;

  CosOfTemp(1) <= not ( ACC(25) xor ACC(24));
  CosOfTemp(0) <= not ( ACC(24) xor ACC(23));

  SinOfTemp(1) <= not ACC(25);
  SinOfTemp(0) <= ACC(24) xor ACC(23);

----//// The value output, when Acc is changed;
  ValueOfCos <= CosOfTemp;
  ValueOfSin <= SinOfTemp;
-------------------////////////----------------

----  process(SampleClk)
----  begin
----     if SampleClk'event and SampleClk='1' then
----	   ValueOfCos <= CosOfTemp;
----     end if;
----  end process;

----  process(SampleClk)
----  begin
----     if SampleClk'event and SampleClk='1' then
----	   ValueOfSin <= SinOfTemp;
----	end if;
----  end process;



end rtl;