digital_correlator.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Digital_Correlator is
    Port ( SampleClk          : in std_logic;
           Reset              : in std_logic;
           DataIn             : in std_logic_vector(1 downto 0);  --mixofcarry's input
		 Carry_Fre          : in std_logic_vector(25 downto 0);	   --carry_dco's input
		 EnableOfCarry_Fre  : in std_logic;						         -- carry_dco's input
           SelOfEL            : in std_logic;		               --epl_shift_register's input
           CodeOfSlew         : in std_logic_vector(10 downto 0);	--slewof_generate's input
           Code_Phase         : in std_logic_vector(25 downto 0);	--code_dco's input
           EnableOfCode_Phase : in std_logic;			            --code_dco's input
		 Dump               : out std_logic;		                  --ca_code_signalofcon's output
		 Sum_I_Tracking     : out std_logic_vector(15 downto 0);	   --accumulate's output
		 Sum_I_Prompt		: out std_logic_vector(15 downto 0);
		 Sum_Q_Tracking	: out std_logic_vector(15 downto 0);
		 Sum_Q_Prompt   	: out std_logic_vector(15 downto 0);
		 Code_Phase_Count   : out std_logic_vector(15 downto 0);	   --ca_code_signalofcon's output
		 Epoch_Count        : out std_logic_vector(15 downto 0)	   --epoch_counters'output
		 );
end Digital_Correlator;

architecture rtl of Digital_Correlator is

	COMPONENT carry_dco
	PORT(
		sampleclk  : IN std_logic;
		reset      : IN std_logic;
		carry_fre  : IN std_logic_vector(25 downto 0);
		enable     : IN std_logic;          
		valueofcos : OUT std_logic_vector(1 downto 0);
		valueofsin : OUT std_logic_vector(1 downto 0)
		);
	END COMPONENT;

	COMPONENT mixofcarry
	PORT(
		sampleclk  : IN std_logic;
		datain     : IN std_logic_vector(1 downto 0);
		ampofcarry : IN std_logic_vector(1 downto 0);          
		dataout    : OUT std_logic_vector(2 downto 0)
		);
	END COMPONENT;

	COMPONENT code_dco
	PORT(
		sampleclk : IN std_logic;
		reset : IN std_logic;
		code_phase : IN std_logic_vector(25 downto 0);
		enable : IN std_logic;
		code_phase_count : IN std_logic_vector(15 downto 0);
		countoftemp      : IN std_logic_vector( 10 downto 0);--IN  integer range 0 to 2045;      
		slewofcount      : IN std_logic_vector( 10 downto 0);--IN  integer range 0 to 2045; 		          
		codeclk2 : OUT std_logic;
		codeclk : OUT std_logic
		);
	END COMPONENT;
	

	COMPONENT ca_code_generator
	PORT(
		codeclk    : IN std_logic;
		loadofreset: IN std_logic;          
		ca_code    : OUT std_logic
		);
	END COMPONENT;

	COMPONENT ca_code_signalofcon
	PORT(
		codeclk         : IN std_logic;
		codeclk2        : IN std_logic;
          slew            : IN std_logic;
		reset           : IN std_logic;          
		load_shift      : OUT std_logic;
		code_phase_count: OUT std_logic_vector(15 downto 0);
		code_end        : OUT std_logic;
		dump            : OUT std_logic
		);
	END COMPONENT;

     COMPONENT slewof_generate
	PORT(
		sampleclk : IN std_logic;
		codeclk2 : IN std_logic;
		rstb : IN std_logic;
		code_end : IN std_logic;
		codeofslew : IN std_logic_vector(10 downto 0);
		countoftemp: OUT std_logic_vector( 10 downto 0);
		slewofcount: OUT std_logic_vector( 10 downto 0);		          
		slew : OUT std_logic
		);
	END COMPONENT;


	COMPONENT epl_shift_register
	PORT(
		codeclk2   : IN std_logic;
		reset      : IN std_logic;
		selofel    : IN std_logic;
		ca_code    : IN std_logic;          
		ca_prompt  : OUT std_logic;
		ca_tracking: OUT std_logic
		);
	END COMPONENT;

	COMPONENT epcoch_counters
	PORT(
		reset : IN std_logic;
		dump : IN std_logic;          
		epoch_count : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	COMPONENT accumulate
	PORT(
		sampleclk : IN std_logic;
		slew      : IN std_logic;
		dump      : IN std_logic;
		datain    : IN std_logic_vector(2 downto 0);
		codein    : IN std_logic;          
		dataout   : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	signal  S_ValueOfCos,S_ValueOfSin     : std_logic_vector(1 downto 0);
	signal  S_I_DataOfBaseBand,S_Q_DataOfBaseBand
	                                      : std_logic_vector(2 downto 0);
	signal  S_CodeClk2,S_CodeClk,
	        S_Load_Shift,
		   S_CA_Code,
		   S_CA_Tracking,
		   S_CA_Prompt,
		   S_Code_End,
		   S_Dump,
		   S_Slew	 :  std_logic;


--------------   Add the control signal of slewof_generate and code_dco ----------
     signal  S_Code_Phase_Count : std_logic_vector(15 downto 0);
	signal  S_CountOfTemp      : std_logic_vector( 10 downto 0);      
	signal  S_SlewOfCount      : std_logic_vector( 10 downto 0); 
--------------   Add the control signal of slewof_generate and code_dco ----------	

	
---------------  Add the Reset of CA_Code_Generator -----------
	signal  S_Load_LfsrOne,S_Load_TempLfsrOne 
	                           : std_logic;
---------------  Add the Reset of CA_Code_Generator -----------


begin

	U1_carry_dco: carry_dco PORT MAP(
		sampleclk  => SampleClk ,
		reset      => Reset,
		carry_fre  => Carry_Fre,
		enable     => EnableOfCarry_Fre,
		valueofcos => S_ValueOfCos,
		valueofsin => S_ValueOfSin
	);


	U2_I_mixofcarry: mixofcarry PORT MAP(
		sampleclk  => SampleClk,
		datain     => DataIn,
		ampofcarry => S_ValueOfCos ,
		dataout    => S_I_DataOfBaseBand
	);

	U2_Q_mixofcarry: mixofcarry PORT MAP(
		sampleclk  => SampleClk,
		datain     => DataIn,
		ampofcarry => S_ValueOfSin,
		dataout    => S_Q_DataOfBaseBand
	);


	U3_code_dco: code_dco PORT MAP(
		sampleclk  => Sampleclk,
		reset      => Reset,
		code_phase => Code_Phase,
		enable     => EnableOfCode_Phase,
		code_phase_count => S_Code_Phase_Count,	   ----
		countoftemp      => S_CountOfTemp,    	   ----
		slewofcount      => S_SlewOfCount,		   ----
		codeclk2   => S_CodeClk2,
		codeclk    => S_CodeClk
	);


	U4_ca_code_generator: ca_code_generator PORT MAP(
		codeclk     => S_CodeClk,
		loadofreset => S_Load_LfsrOne,--S_Load_Shift,
		ca_code     => S_CA_Code
	);


---------------  Add test the Reset of CA_Code_Generator -----------

	process(S_CodeClk2)
	begin
	   if S_CodeClk2'event and S_CodeClk2='0' then
	         S_Load_TempLfsrOne <= not S_Load_Shift;
-----///// The following is identified with the above ;//////-------
----	      if S_Load_Shift='1' then
----		    S_Load_LfsrOne <= '0';
----           else
----		    S_Load_LfsrOne <= '1';
----           end if;
        end if;
     end process;
	S_Load_LfsrOne <= S_Load_TempLfsrOne or S_Load_Shift;

---------------  Add test the Reset of CA_Code_Generator -----------


	U5_ca_code_signalofcon: ca_code_signalofcon PORT MAP(
		codeclk    => S_CodeClk,
		codeclk2   => S_CodeClk2,
		Slew       => S_Slew,
		reset      => Reset,
		load_shift => S_load_shift,
		code_phase_count => S_Code_Phase_Count,
		code_end   => S_Code_End,
		dump       => S_Dump
	);

	Code_Phase_Count <= S_Code_Phase_Count;

---------------------////////////////////////
          Dump <= S_Dump;
---------------------////////////////////////

	u3_slewof_generate: slewof_generate PORT MAP(
		sampleclk  => SampleClk,
		codeclk2   => S_CodeClk2,
		rstb       => Reset,
		code_end   => S_Code_End,
		codeofslew => CodeOfSlew,
		countoftemp=> S_CountOfTemp,
		slewofcount=> S_SlewOfCount,	
		slew       => S_Slew
	);

	U7_epl_shift_register: epl_shift_register PORT MAP(
		codeclk2   => S_CodeClk2,
		reset      => Reset,
		selofel    => SelOfEL,
		ca_code    => S_CA_Code,
		ca_prompt  => S_CA_Prompt,
		ca_tracking=> S_CA_Tracking
	);

	U8_epcoch_counters: epcoch_counters PORT MAP(
		reset      => Reset,
		dump       => S_Dump,
		epoch_count=> Epoch_Count
	);

	U9_I_Tracking_accumulate: accumulate PORT MAP(
		sampleclk  => SampleClk,
		slew       => S_Slew,
		dump       => S_Dump,
		datain     => S_I_DataOfBaseBand,
		codein     => S_CA_Tracking,
		dataout    => Sum_I_Tracking 
	);

	U9_I_Prompt_accumulate: accumulate PORT MAP(
		sampleclk  => SampleClk,
		slew       => S_Slew,
		dump       => S_Dump,
		datain     => S_I_DataOfBaseBand,
		codein     => S_CA_Prompt,
		dataout    => Sum_I_Prompt 
	);

	U9_Q_Tracking_accumulate: accumulate PORT MAP(
		sampleclk => SampleClk ,
		slew      => S_Slew,
		dump      => S_Dump,
		datain    => S_Q_DataOfBaseBand,
		codein    => S_CA_Tracking,
		dataout   => Sum_Q_Tracking
	);

	U9_Q_Prompt_accumulate: accumulate PORT MAP(
		sampleclk => SampleClk,
		slew      => S_Slew,
		dump      => S_Dump,
		datain    => S_Q_DataOfBaseBand,
		codein    => S_CA_Prompt,
		dataout   => Sum_Q_Prompt 
	);



end rtl;