hardtest_digital_correlation.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity HardTest_Digital_Correlation is
    Port ( Clk          : in std_logic;
------           DataIn             : in std_logic_vector(11 downto 0);
----------------------------/////////////////////-----------------------
           DataIn             : in std_logic_vector(1 downto 0);    
----------------------------/////////////////////-----------------------       
----		 Carry_Fre          : in std_logic_vector(25 downto 0);
----		 EnableOfCarry_Fre  : in std_logic;
----       SelOfEL            : in std_logic;
----           CodeOfSlew         : in std_logic_vector(10 downto 0);
----           Code_Phase         : in std_logic_vector(25 downto 0);
----           EnableOfCode_Phase : in std_logic;
------       AD_Clk             : out std_logic;
------		 AD_OE              : out std_logic;
------		 AD_PD              : out std_logic;
       SampleClk          : out std_logic;
		 Clk_10M				  : out std_logic;
		 Sum_I_Tracking     : out std_logic_vector(15 downto 0);
----		 Sum_I_Prompt		: out std_logic_vector(15 downto 0);
		 Sum_Q_Tracking	: out std_logic_vector(15 downto 0);
----		 Sum_Q_Prompt   	: out std_logic_vector(15 downto 0);
       Detect             : out std_logic;
		 Code_Phase_Count   : out std_logic_vector(15 downto 0);
		 Epoch_Count        : out std_logic_vector(15 downto 0)
		 );
end HardTest_Digital_Correlation;

architecture rtl of HardTest_Digital_Correlation is


	COMPONENT clockgenerator
	PORT(
		clk : IN std_logic;          
		sampleclk : OUT std_logic;
		clk_10m : OUT std_logic
		);
	END COMPONENT;

	COMPONENT datatransfer_ad
	PORT(
		ad_clk    : IN std_logic;
		datain    : IN std_logic_vector(11 downto 0);          
		ad_oe     : OUT std_logic;
		ad_pd     : OUT std_logic;
		data_gps  : OUT std_logic_vector(1 downto 0)
		);
	END COMPONENT;


	COMPONENT digital_correlator
	PORT(
		sampleclk         : IN std_logic;
		reset             : IN std_logic;
		datain            : IN std_logic_vector(1 downto 0);
		carry_fre         : IN std_logic_vector(25 downto 0);
		enableofcarry_fre : IN std_logic;
		selofel           : IN std_logic;
		codeofslew        : IN std_logic_vector(10 downto 0);
		code_phase        : IN std_logic_vector(25 downto 0);
		enableofcode_phase: IN std_logic;
		dump              : OUT std_logic;          
		sum_i_tracking    : OUT std_logic_vector(15 downto 0);
		sum_i_prompt      : OUT std_logic_vector(15 downto 0);
		sum_q_tracking    : OUT std_logic_vector(15 downto 0);
		sum_q_prompt      : OUT std_logic_vector(15 downto 0);
		code_phase_count  : OUT std_logic_vector(15 downto 0);
		epoch_count       : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

	COMPONENT debug_detect_peakvalue
	PORT(
		sampleclk : IN std_logic;
		enable_detect : IN std_logic;
		sum_i_prompt : IN std_logic_vector(15 downto 0);
		sum_q_prompt : IN std_logic_vector(15 downto 0);          
		detect : OUT std_logic;
		codeofslew : OUT std_logic_vector(10 downto 0)
		);
	END COMPONENT;


	signal Count                : integer range 0 to 15;
	signal S_SampleClk          : std_logic;
	signal S_Clk_10M				 : std_logic;
	signal S_Data_Gps           : std_logic_vector(1 downto 0);
	signal S_Reset              : std_logic;
	signal S_EnableOfCarry_Fre  : std_logic;
   signal S_Carry_Fre          : std_logic_vector(25 downto 0);
	signal S_SelOfEL            : std_logic;
   signal S_EnableOfCode_Phase : std_logic;
	signal S_Dump               : std_logic;
   signal S_Code_Phase         : std_logic_vector(25 downto 0);
----	signal S_Sum_I_Tracking     : std_logic_vector(15 downto 0);
	signal S_Sum_I_Prompt	   : std_logic_vector(15 downto 0);
----	signal S_Sum_Q_Tracking	   : std_logic_vector(15 downto 0);
	signal S_Sum_Q_Prompt   	   : std_logic_vector(15 downto 0);
   signal S_CodeOfSlew         : std_logic_vector(10 downto 0);

begin


   process(Clk)
	begin
	   if Clk'event and Clk='1' then
	      if Count = 10 then
		    Count <= Count;
           else
		    Count <= Count + 1;
           end if;

		 if Count = 10 then
		    S_Reset <= '1';
           else
		    S_Reset <= '0';
           end if;
         end if;
   end process;



	U1_clockgenerator: clockgenerator PORT MAP(
		clk       => Clk,
		sampleclk => S_SampleClk,
		clk_10m   => S_Clk_10M
	);

	SampleClk <= S_SampleClk;
	Clk_10M   <= S_Clk_10M;


----------	U2_datatransfer_ad: datatransfer_ad PORT MAP(
----------		ad_clk    =>  S_SampleClk,
----------		datain    =>  DataIn,
----------		ad_oe     =>  AD_OE,
----------		ad_pd     =>  AD_PD,
----------		data_gps  =>  S_Data_Gps
----------	);

----------	   AD_Clk	<= S_SampleClk;

-------------  /////////////  ----------------
		S_EnableOfCarry_Fre  <= '0';
		S_Carry_Fre          <= (others=>'0');
		S_SelOfEL            <= '0';    ------/////  Early Code;
      S_EnableOfCode_Phase <= '0';
      S_Code_Phase         <= (others=>'0');
-------------  /////////////  ----------------



		S_Data_Gps <= DataIn;

	U3_digital_correlator: digital_correlator PORT MAP(
		sampleclk         => S_SampleClk,
		reset             => S_Reset,
		datain            => S_Data_Gps,
		carry_fre         => S_Carry_Fre,
		enableofcarry_fre => S_EnableOfCarry_Fre,
		selofel           => S_SelOfEL,
		-----------////////----------
		codeofslew        => S_CodeOfSlew,		 
          -----------////////----------
		code_phase        => S_Code_Phase,
		enableofcode_phase=> S_EnableOfCode_Phase,
		dump              => S_Dump,
		sum_i_tracking    => Sum_I_Tracking,
		sum_i_prompt      => S_Sum_I_Prompt,
		sum_q_tracking    => Sum_Q_Tracking,
		sum_q_prompt      => S_Sum_Q_Prompt,
		code_phase_count  => Code_Phase_Count,	---- the output;
		epoch_count       => Epoch_Count		---- the output;
	);

	U4_debug_detect_peakvalue: debug_detect_peakvalue PORT MAP(
		sampleclk         => S_SampleClk,
		enable_detect     => S_Dump,
		sum_i_prompt      => S_Sum_I_Prompt,
		sum_q_prompt      => S_Sum_Q_Prompt,
		detect            => Detect,
		codeofslew        => S_CodeOfSlew
	);



end rtl;