code_dco.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

---- Simulation is right;

---- Date: 2004,8,15;
---- //// Code_Dco;
---- //// The importan parameter:
---- //// 1) the Frequency of Carrier : 
----         88.54/63 = 1.4053968253968253968253968253968;
---- //// 2) the SampleClk : 
----         40/7     = 5.7142857142857142857142857142857;
---- //// 3) the standard Code Word : 
----         ((2.046)/(40/7))*(2^26)=24028328.755200000000000000000003;
----   ====>>> "01011011101010010010101000";

---- //// Enable : active when high, indicate get the Code_Phase from the register of the Interface;
----      the signal should be provided by the Interface of FPGA to DSP;
----      the signal should ensure the data of Code_Phase be read correctly and  only be read one time,
----      and when Enable is low , the data of Coder_Phase should be Zeros by the signal of Clr of the
----      Interface;
---- //// Enable shoulde be considered carefully;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Code_Dco is
    Port ( SampleClk : in std_logic;
           Reset     : in std_logic;
		 Code_Phase: in std_logic_vector( 25 downto 0);
		 Enable    : in std_logic;	  ---- Should be deleted;//////
		 Code_Phase_Count : in std_logic_vector(15 downto 0);
		 CountOfTemp : in std_logic_vector(10 downto 0);-- integer range 0 to 2045;      
		 SlewOfCount : in std_logic_vector(10 downto 0);-- integer range 0 to 2045; 
           CodeClk2  : out std_logic;
           CodeClk   : out std_logic);
end Code_Dco;

architecture rtl of Code_Dco is

   signal  ACC  :  std_logic_vector( 25 downto 0);
   signal  PW   :  std_logic_vector( 25 downto 0);
   signal  CodeClk2OfTemp,CodeClkOfTemp
                :  std_logic;

begin

  process(SampleClk,Reset)
  begin
     if Reset='0' then
	   PW <= --------"00101101110101001001010100";
		   "01011011101010010010101000";		-------- Generate 2.046MHz;
	elsif SampleClk'event and SampleClk='1' then
----//// Should be replaced by the ---- ////////-----
	      if Enable='1' then
	         PW <= PW + Code_Phase;
           end if;
----//// Should be replaced by the ---- ////////-----
----       if Enable='1' then
----		    PW <= Code_Phase;
----		 end if;
     end if;
  end process;
  
  process (SampleClk,Reset)
  begin
     if Reset='0' then
	     ACC <= (others=>'0');
	elsif SampleClk'event and SampleClk='1' then
	       ACC <= ACC + PW;
     end if;
  end process;

  CodeClk2OfTemp <= ACC(25);

  process(CodeClk2OfTemp,Reset)
  begin
     if Reset='0' then
	   CodeClkOfTemp <= '0';
	elsif CodeClk2OfTemp'event and CodeClk2OfTemp='1' then
	    if Code_Phase_Count="0000000000000000" then
	       if CountOfTemp="0000000000" then
		      CodeClkOfTemp <= not CodeClkOfTemp;
            else
		      CodeClkOfTemp <= '0';
            end if;
         else
	       if SlewOfCount="0000000000" or SlewOfCount="0000000001" then
		      CodeClkOfTemp <= not CodeClkOfTemp;
	       else
	           CodeClkOfTemp <= CodeClkOfTemp;
	       end if;
	    end if;		                    		     		
	       
     end if;
  end process;

  CodeClk2 <=  CodeClk2OfTemp;
  CodeClk  <=  CodeClkOfTemp ;

end rtl;