accumulate.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

----//// Simulation is right;
----   not test the process of Acc;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity Accumulate is
    Port ( SampleClk : in std_logic;
           Slew : in std_logic;
           Dump : in std_logic;
           DataIn : in std_logic_vector(2 downto 0);
           CodeIn : in std_logic;
----		 DataOfTest1 : out std_logic_vector(2 downto 0);
----		 DataOfTest2 : out std_logic_vector(3 downto 0);
           DataOut : out std_logic_vector(15 downto 0));
end Accumulate;

architecture rtl of Accumulate is

    signal DataOfTemp : std_logic_vector(2 downto 0);
    signal DataOf2Com : std_logic_vector(3 downto 0);
    signal Data       : signed(3 downto 0);
    signal Reg_Dump	  : std_logic;

begin 


    GetDataOfSourceCode:
    process (DataIn(1 downto 0))
    begin
      case DataIn(1 downto 0) is
        when "00"   => DataOfTemp <= "001";
        when "01"   => DataOfTemp <= "010";
        when "10"   => DataOfTemp <= "011";
        when "11"   => DataOfTemp <= "110";
	   when others => NULL;
      end case;
    end process;

----- Check the DataOfTemp:
----- the SourceCode when select one of four;
-----    DataOfTest1  <=  DataOfTemp;

----- Check the DataOf2Com:
----- the 2Complement Code:
-----    DataOfTest2 <= DataOf2Com;    


    GetDataOf2Complement:
    DataOf2Com   <=   '0'&DataOfTemp  when  DataIn(2)='1' else
                      ('1'&( not DataOfTemp)) + 1; 

    Data <= Signed(DataOf2Com);

    process(SampleClk)
----    variable V_Dump	: std_logic;
    variable Acc    : signed(15 downto 0);
    begin
       if SampleClk'event and SampleClk='1' then
	        Reg_Dump <= Dump;
----	        V_Dump := Dump;
----////----	     if Slew='1' then
----////----////		   if Dump='1' then
             if Reg_Dump='0' and Dump='1' then 
		      DataOut <= std_logic_vector(Acc);
			 Acc     := (others=>'0');
             else
------		      if Slew='1'and Dump='0' then   ----////----	  Revise 9,18
		      if Slew='1' then   ----////----
		          if CodeIn='0' then 
		              Acc := Acc + Data;
                    else
			         Acc := Acc - Data;
                    end if;
                end if;		     ----////----
             end if;
----////----          end if;
       end if;
    end process;

end rtl;