epcoch_counters.vhd

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---- // Epcoch_Counters;
---- // 
----   Epoch_Count(13 downto 8) <= CountersOfEpochH;   
----   Epoch_Count( 4 downto 0) <= CountersOfEpochL;    
----    

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Epcoch_Counters is
    Port ( Reset            : in std_logic;  ---- the Reset of software;
--           SampleClk : in std_logic;
           Dump             : in std_logic;
		 Epoch_Count      : out std_logic_vector( 15 downto 0)
		 );
end Epcoch_Counters;

architecture rtl of Epcoch_Counters is

    signal Count_01ms       : integer range 0 to 19;
    signal Count_20ms       : integer range 0 to 49;
    signal CountersOfEpochH : std_logic_vector( 5 downto 0);
    signal CountersOfEpochL : std_logic_vector( 4 downto 0); 

begin

   process(Dump,Reset)
   begin
      if Reset='0' then
	     Count_01ms <= 0;
		Count_20ms <= 0;
      elsif Dump'event and Dump='1' then
	       if Count_01ms=19 then
		     Count_01ms <= 0;
			if Count_20ms=49 then
			   Count_20ms <= 0;
               else
			   Count_20ms <= Count_20ms + 1;
               end if;
		  else
		     Count_01ms <= Count_01ms + 1;
		  end if;
      end if;
   end process;

   CountersOfEpochH <= CONV_STD_LOGIC_VECTOR (Count_20ms, 6);
   CountersOfEpochL <= CONV_STD_LOGIC_VECTOR (Count_01ms, 5);

   Epoch_Count <= "00"&CountersOfEpochH&"000"&CountersOfEpochL;  	       
			     
end rtl;