clockgenerator.vhd

VHDLfullCODEforCAcodeGenerator.rar为CA码发生器的完整VHDL程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity ClockGenerator is
    Port ( Clk : in std_logic;
           SampleClk : out std_logic;
			  Clk_10M   : out std_logic
		 );
end ClockGenerator;

architecture rtl of ClockGenerator is

  signal  Count1 : integer range 0 to 6;
  signal  Count2 : integer range 0 to 1;
  signal  Temp_Clk : std_logic;	--在这个信号不进行初始化时，行为仿真结果Clk_10M恒为U,因此应在此处
												  --进行初始化
begin


  process(Clk)
  begin

    if Clk'event and Clk='1' then

       if  Count1=6  then
	      Count1 <= 0 ;
       else 
	      Count1 <= Count1 + 1;
       end if;

       if  Count2=1  then
	      Count2 <= 0 ;
       else 
	      Count2 <= Count2 + 1;
       end if;

	    if  Count1=3 then
	      SampleClk <= '0';
       end if;
	    if  Count1=6 then 
	      SampleClk <= '1';
       end if;

	    if  Count2=1 then
	      Temp_Clk <= not Temp_Clk;
       end if;

    end if;		 
	 
  end process;
 	  Clk_10M <= Temp_Clk; 

end rtl;