📄 ptos.v
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module PTOS(clk,par_in,int_mcu,serial,bclk,sync,cpld_rst,codec_rst,fmt0,fmt1,fmt2,mcu_ctrl) ;
input clk;
input mcu_ctrl;
input [15:0]par_in ;
output serial;
output sync; //44.1KHZ to CODEC
output bclk;
output int_mcu; //88.2KHZ to MCU
input cpld_rst;
output codec_rst;
output fmt0,fmt1,fmt2;
reg bclk;
reg serial;
reg sync;
reg[15:0]par;
reg [3:0]count;
reg [3:0]fd;
reg d_syn;
assign codec_rst=cpld_rst;
assign fmt0=(mcu_ctrl==0)?par_in[0]:1;
assign fmt1=(mcu_ctrl==0)?par_in[1]:1;
assign fmt2=(mcu_ctrl==0)?par_in[2]:1;
assign int_mcu=!d_syn;
initial begin fd=0;end
// add your declarations here
always @(posedge clk)
begin
fd<=fd+1;
if(fd==7) fd<=0;
if(fd<4) bclk<=0;
else bclk<=1;
end
always @(negedge bclk)
begin
count<=count+1;
d_syn<=!count[3]; //BLCK/16=88.2K HZ d_syn
case (count[3:0])
4'b0000: serial<=par[15];
4'b0001: serial<=par[14];
4'b0010: serial<=par[13];
4'b0011: serial<=par[12];
4'b0100: serial<=par[11];
4'b0101: serial<=par[10];
4'b0110: serial<=par[9];
4'b0111: serial<=par[8];
4'b1000: serial<=par[7];
4'b1001: serial<=par[6];
4'b1010: serial<=par[5];
4'b1011: serial<=par[4];
4'b1100: serial<=par[3];
4'b1101: serial<=par[2];
4'b1110: serial<=par[1];
4'b1111: begin
serial<=par[0];
par<=par_in;
end
endcase
// add your code here
end
always @(posedge d_syn) //sync = int_mcu/2 =88.2K/2=44.1KHZ
sync<=!sync;
endmodule
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