startup.s

lpc2294 Bootloader Linux嵌入开发

PINSEL0     EQU 0xE002C000
PINSEL2     EQU 0xE002C014

BCFG0       EQU 0xFFE00000
BCFG1       EQU 0xFFE00004
BCFG2       EQU 0xFFE00008
BCFG3       EQU 0xFFE0000C


MASK_MODE		EQU		0x0000003F
MODE_SVC32		EQU		0x00000013

I_BIT           EQU     0x80 ; when I bit is set, IRQ is disabled
F_BIT           EQU     0x40 ; when F bit is set, FIQ is disabled


   	IMPORT  main        
	IMPORT  TargetResetInit
	
    CODE32

    AREA    vectors,CODE,READONLY
        ENTRY

Reset
        LDR     PC, ResetAddr
        LDR     PC, UndefinedAddr
        LDR     PC, SWI_Addr
        LDR     PC, PrefetchAddr
        LDR     PC, DataAbortAddr
        DCD     0xb9205f80
        LDR     PC, IRQ_Addr
        LDR     PC, FIQ_Addr

ResetAddr			DCD		ResetInit
UndefinedAddr       DCD     0x81000004
SWI_Addr            DCD     0x81000008
PrefetchAddr        DCD     0x8100000c
DataAbortAddr       DCD     0x81000010
Nouse               DCD     0
IRQ_Addr            DCD     0x81000018
FIQ_Addr            DCD     0x8100001c

;********************************************************************************************************/
ResetInit

;disable interrupts in CPU and switch to SVC32 mode

	MRS	r0, cpsr
	BIC	r0, r0, #MASK_MODE
	ORR	r0, r0, #MODE_SVC32
	ORR r0, r0, #I_BIT
	ORR r0, r0, #F_BIT
	MSR	cpsr_c, r0
	
;Initialzie external memory controller according to board setup

        LDR     R0, =PINSEL0		
        LDR     R1, =0x80000005			;ext2 for ethernet, uart0
        STR     R1, [R0]
        
        LDR     R0, =PINSEL2
        LDR     R1, =0x0f814924			;config bank0,1,2,3
        STR     R1, [R0]

        LDR     R0, =BCFG0				;bank0: 32bit, external flash
        LDR     R1, =0x2000ffef			;set to high speed for loading kernel
        STR     R1, [R0]

        LDR     R0, =BCFG1				;bank1: 32bit, external pSRAM
        LDR     R1, =0x2000ffef			;set to high speed for loading kernel
        STR     R1, [R0]

        LDR     R0, =BCFG2
        LDR     R1, =0x10007c67			;bank2: 16bit, Ethernet
        STR     R1, [R0]

        LDR     R0, =BCFG3
        LDR     R1, =0x0000ffef			;bank3:8bit, LCD
        STR     R1, [R0]
        
        LDR		SP, =0x40003000
        
        BL      TargetResetInit         
                                        
        BL      main 					;Jump to C entrance
        


        LDR     R0, =BCFG1				;bank1: 32bit, external pSRAM
        LDR     R1, =0x20007c67			;set to low speed for stability
        STR     R1, [R0]

        LDR		PC, =0x81008000			;jump to uClinux start up

        END


;/*********************************************************************************************************
;**                            End Of File
;********************************************************************************************************/