de2_top.hier_info

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

iDIG[14] => iDIG[14]~17.IN1
iDIG[15] => iDIG[15]~16.IN1
iDIG[16] => iDIG[16]~15.IN1
iDIG[17] => iDIG[17]~14.IN1
iDIG[18] => iDIG[18]~13.IN1
iDIG[19] => iDIG[19]~12.IN1
iDIG[20] => iDIG[20]~11.IN1
iDIG[21] => iDIG[21]~10.IN1
iDIG[22] => iDIG[22]~9.IN1
iDIG[23] => iDIG[23]~8.IN1
iDIG[24] => iDIG[24]~7.IN1
iDIG[25] => iDIG[25]~6.IN1
iDIG[26] => iDIG[26]~5.IN1
iDIG[27] => iDIG[27]~4.IN1
iDIG[28] => iDIG[28]~3.IN1
iDIG[29] => iDIG[29]~2.IN1
iDIG[30] => iDIG[30]~1.IN1
iDIG[31] => iDIG[31]~0.IN1


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u0
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u1
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u2
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u3
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u4
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u5
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u6
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u7
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|DE2_TOP|dds:u1|reg2:b2v_inst4
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
d[8] => q[8]~reg0.DATAIN
d[9] => q[9]~reg0.DATAIN
clk => q[0]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[6]~reg0.CLK
clk => q[7]~reg0.CLK
clk => q[8]~reg0.CLK
clk => q[9]~reg0.CLK
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_TOP|dds:u1|adder:b2v_inst5
a[0] => Add0.IN10
a[1] => Add0.IN9
a[2] => Add0.IN8
a[3] => Add0.IN7
a[4] => Add0.IN6
a[5] => Add0.IN5
a[6] => Add0.IN4
a[7] => Add0.IN3
a[8] => Add0.IN2
a[9] => Add0.IN1
b[0] => Add0.IN20
b[1] => Add0.IN19
b[2] => Add0.IN18
b[3] => Add0.IN17
b[4] => Add0.IN16
b[5] => Add0.IN15
b[6] => Add0.IN14
b[7] => Add0.IN13
b[8] => Add0.IN12
b[9] => Add0.IN11
clk => s[0]~reg0.CLK
clk => s[1]~reg0.CLK
clk => s[2]~reg0.CLK
clk => s[3]~reg0.CLK
clk => s[4]~reg0.CLK
clk => s[5]~reg0.CLK
clk => s[6]~reg0.CLK
clk => s[7]~reg0.CLK
clk => s[8]~reg0.CLK
clk => s[9]~reg0.CLK
s[0] <= s[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[1] <= s[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[2] <= s[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[3] <= s[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[4] <= s[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[5] <= s[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[6] <= s[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[7] <= s[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[8] <= s[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
s[9] <= s[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_TOP|dds:u1|sinrom:b2v_inst8
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]


|DE2_TOP|dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_71a1:auto_generated.address_a[0]
address_a[1] => altsyncram_71a1:auto_generated.address_a[1]
address_a[2] => altsyncram_71a1:auto_generated.address_a[2]
address_a[3] => altsyncram_71a1:auto_generated.address_a[3]
address_a[4] => altsyncram_71a1:auto_generated.address_a[4]
address_a[5] => altsyncram_71a1:auto_generated.address_a[5]
address_a[6] => altsyncram_71a1:auto_generated.address_a[6]
address_a[7] => altsyncram_71a1:auto_generated.address_a[7]
address_a[8] => altsyncram_71a1:auto_generated.address_a[8]
address_a[9] => altsyncram_71a1:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_71a1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_71a1:auto_generated.q_a[0]
q_a[1] <= altsyncram_71a1:auto_generated.q_a[1]
q_a[2] <= altsyncram_71a1:auto_generated.q_a[2]
q_a[3] <= altsyncram_71a1:auto_generated.q_a[3]
q_a[4] <= altsyncram_71a1:auto_generated.q_a[4]
q_a[5] <= altsyncram_71a1:auto_generated.q_a[5]
q_a[6] <= altsyncram_71a1:auto_generated.q_a[6]
q_a[7] <= altsyncram_71a1:auto_generated.q_a[7]
q_a[8] <= altsyncram_71a1:auto_generated.q_a[8]
q_a[9] <= altsyncram_71a1:auto_generated.q_a[9]
q_b[0] <= <GND>


|DE2_TOP|dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated
address_a[0] => altsyncram_rsf2:altsyncram1.address_a[0]
address_a[1] => altsyncram_rsf2:altsyncram1.address_a[1]
address_a[2] => altsyncram_rsf2:altsyncram1.address_a[2]
address_a[3] => altsyncram_rsf2:altsyncram1.address_a[3]
address_a[4] => altsyncram_rsf2:altsyncram1.address_a[4]
address_a[5] => altsyncram_rsf2:altsyncram1.address_a[5]
address_a[6] => altsyncram_rsf2:altsyncram1.address_a[6]
address_a[7] => altsyncram_rsf2:altsyncram1.address_a[7]
address_a[8] => altsyncram_rsf2:altsyncram1.address_a[8]
address_a[9] => altsyncram_rsf2:altsyncram1.address_a[9]
clock0 => altsyncram_rsf2:altsyncram1.clock0
q_a[0] <= altsyncram_rsf2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_rsf2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_rsf2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_rsf2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_rsf2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_rsf2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_rsf2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_rsf2:altsyncram1.q_a[7]
q_a[8] <= altsyncram_rsf2:altsyncram1.q_a[8]
q_a[9] <= altsyncram_rsf2:altsyncram1.q_a[9]


|DE2_TOP|dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[0] => ram_block3a8.PORTAADDR
address_a[0] => ram_block3a9.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[1] => ram_block3a8.PORTAADDR1
address_a[1] => ram_block3a9.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[2] => ram_block3a8.PORTAADDR2
address_a[2] => ram_block3a9.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[3] => ram_block3a8.PORTAADDR3
address_a[3] => ram_block3a9.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[4] => ram_block3a8.PORTAADDR4
address_a[4] => ram_block3a9.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[5] => ram_block3a8.PORTAADDR5
address_a[5] => ram_block3a9.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[6] => ram_block3a8.PORTAADDR6
address_a[6] => ram_block3a9.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_a[7] => ram_block3a8.PORTAADDR7
address_a[7] => ram_block3a9.PORTAADDR7
address_a[8] => ram_block3a0.PORTAADDR8
address_a[8] => ram_block3a1.PORTAADDR8
address_a[8] => ram_block3a2.PORTAADDR8
address_a[8] => ram_block3a3.PORTAADDR8
address_a[8] => ram_block3a4.PORTAADDR8
address_a[8] => ram_block3a5.PORTAADDR8
address_a[8] => ram_block3a6.PORTAADDR8
address_a[8] => ram_block3a7.PORTAADDR8