de2_top.hier_info

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

GPIO_1[4] <= GPIO_1~67
GPIO_1[5] <= GPIO_1~66
GPIO_1[6] <= GPIO_1~65
GPIO_1[7] <= GPIO_1~64
GPIO_1[8] <= GPIO_1~63
GPIO_1[9] <= GPIO_1~62
GPIO_1[10] <= GPIO_1~61
GPIO_1[11] <= GPIO_1~60
GPIO_1[12] <= GPIO_1~59
GPIO_1[13] <= GPIO_1~58
GPIO_1[14] <= GPIO_1~57
GPIO_1[15] <= GPIO_1~56
GPIO_1[16] <= GPIO_1~55
GPIO_1[17] <= GPIO_1~54
GPIO_1[18] <= GPIO_1~53
GPIO_1[19] <= GPIO_1~52
GPIO_1[20] <= GPIO_1~51
GPIO_1[21] <= GPIO_1~50
GPIO_1[22] <= GPIO_1~49
GPIO_1[23] <= GPIO_1~48
GPIO_1[24] <= GPIO_1~47
GPIO_1[25] <= GPIO_1~46
GPIO_1[26] <= GPIO_1~45
GPIO_1[27] <= GPIO_1~44
GPIO_1[28] <= GPIO_1~43
GPIO_1[29] <= GPIO_1~42
GPIO_1[30] <= GPIO_1~41
GPIO_1[31] <= GPIO_1~40
GPIO_1[32] <= GPIO_1~39
GPIO_1[33] <= GPIO_1~38
GPIO_1[34] <= GPIO_1~37
GPIO_1[35] <= GPIO_1~36


|DE2_TOP|dds:u1
clk => clk~0.IN8
en => en~0.IN1
reset => reset~0.IN1
k[0] => k[0]~9.IN1
k[1] => k[1]~8.IN1
k[2] => k[2]~7.IN1
k[3] => k[3]~6.IN1
k[4] => k[4]~5.IN1
k[5] => k[5]~4.IN1
k[6] => k[6]~3.IN1
k[7] => k[7]~2.IN1
k[8] => k[8]~1.IN1
k[9] => k[9]~0.IN1
p[0] => p[0]~9.IN1
p[1] => p[1]~8.IN1
p[2] => p[2]~7.IN1
p[3] => p[3]~6.IN1
p[4] => p[4]~5.IN1
p[5] => p[5]~4.IN1
p[6] => p[6]~3.IN1
p[7] => p[7]~2.IN1
p[8] => p[8]~1.IN1
p[9] => p[9]~0.IN1
hex0[0] <= SEG7_LUT_8:b2v_inst3.oSEG0
hex0[1] <= SEG7_LUT_8:b2v_inst3.oSEG0
hex0[2] <= SEG7_LUT_8:b2v_inst3.oSEG0
hex0[3] <= SEG7_LUT_8:b2v_inst3.oSEG0
hex0[4] <= SEG7_LUT_8:b2v_inst3.oSEG0
hex0[5] <= SEG7_LUT_8:b2v_inst3.oSEG0
hex0[6] <= SEG7_LUT_8:b2v_inst3.oSEG0
hex1[0] <= SEG7_LUT_8:b2v_inst3.oSEG1
hex1[1] <= SEG7_LUT_8:b2v_inst3.oSEG1
hex1[2] <= SEG7_LUT_8:b2v_inst3.oSEG1
hex1[3] <= SEG7_LUT_8:b2v_inst3.oSEG1
hex1[4] <= SEG7_LUT_8:b2v_inst3.oSEG1
hex1[5] <= SEG7_LUT_8:b2v_inst3.oSEG1
hex1[6] <= SEG7_LUT_8:b2v_inst3.oSEG1
hex2[0] <= SEG7_LUT_8:b2v_inst3.oSEG2
hex2[1] <= SEG7_LUT_8:b2v_inst3.oSEG2
hex2[2] <= SEG7_LUT_8:b2v_inst3.oSEG2
hex2[3] <= SEG7_LUT_8:b2v_inst3.oSEG2
hex2[4] <= SEG7_LUT_8:b2v_inst3.oSEG2
hex2[5] <= SEG7_LUT_8:b2v_inst3.oSEG2
hex2[6] <= SEG7_LUT_8:b2v_inst3.oSEG2
hex3[0] <= SEG7_LUT_8:b2v_inst3.oSEG3
hex3[1] <= SEG7_LUT_8:b2v_inst3.oSEG3
hex3[2] <= SEG7_LUT_8:b2v_inst3.oSEG3
hex3[3] <= SEG7_LUT_8:b2v_inst3.oSEG3
hex3[4] <= SEG7_LUT_8:b2v_inst3.oSEG3
hex3[5] <= SEG7_LUT_8:b2v_inst3.oSEG3
hex3[6] <= SEG7_LUT_8:b2v_inst3.oSEG3
hex4[0] <= SEG7_LUT_8:b2v_inst3.oSEG4
hex4[1] <= SEG7_LUT_8:b2v_inst3.oSEG4
hex4[2] <= SEG7_LUT_8:b2v_inst3.oSEG4
hex4[3] <= SEG7_LUT_8:b2v_inst3.oSEG4
hex4[4] <= SEG7_LUT_8:b2v_inst3.oSEG4
hex4[5] <= SEG7_LUT_8:b2v_inst3.oSEG4
hex4[6] <= SEG7_LUT_8:b2v_inst3.oSEG4
hex5[0] <= SEG7_LUT_8:b2v_inst3.oSEG5
hex5[1] <= SEG7_LUT_8:b2v_inst3.oSEG5
hex5[2] <= SEG7_LUT_8:b2v_inst3.oSEG5
hex5[3] <= SEG7_LUT_8:b2v_inst3.oSEG5
hex5[4] <= SEG7_LUT_8:b2v_inst3.oSEG5
hex5[5] <= SEG7_LUT_8:b2v_inst3.oSEG5
hex5[6] <= SEG7_LUT_8:b2v_inst3.oSEG5
hex6[0] <= SEG7_LUT_8:b2v_inst3.oSEG6
hex6[1] <= SEG7_LUT_8:b2v_inst3.oSEG6
hex6[2] <= SEG7_LUT_8:b2v_inst3.oSEG6
hex6[3] <= SEG7_LUT_8:b2v_inst3.oSEG6
hex6[4] <= SEG7_LUT_8:b2v_inst3.oSEG6
hex6[5] <= SEG7_LUT_8:b2v_inst3.oSEG6
hex6[6] <= SEG7_LUT_8:b2v_inst3.oSEG6
hex7[0] <= SEG7_LUT_8:b2v_inst3.oSEG7
hex7[1] <= SEG7_LUT_8:b2v_inst3.oSEG7
hex7[2] <= SEG7_LUT_8:b2v_inst3.oSEG7
hex7[3] <= SEG7_LUT_8:b2v_inst3.oSEG7
hex7[4] <= SEG7_LUT_8:b2v_inst3.oSEG7
hex7[5] <= SEG7_LUT_8:b2v_inst3.oSEG7
hex7[6] <= SEG7_LUT_8:b2v_inst3.oSEG7


|DE2_TOP|dds:u1|sum99:b2v_inst
k[0] => Add0.IN10
k[1] => Add0.IN9
k[2] => Add0.IN8
k[3] => Add0.IN7
k[4] => Add0.IN6
k[5] => Add0.IN5
k[6] => Add0.IN4
k[7] => Add0.IN3
k[8] => Add0.IN2
k[9] => Add0.IN1
clk => temp[0].CLK
clk => temp[1].CLK
clk => temp[2].CLK
clk => temp[3].CLK
clk => temp[4].CLK
clk => temp[5].CLK
clk => temp[6].CLK
clk => temp[7].CLK
clk => temp[8].CLK
clk => temp[9].CLK
en => temp[0].ENA
en => temp[1].ENA
en => temp[2].ENA
en => temp[3].ENA
en => temp[4].ENA
en => temp[5].ENA
en => temp[6].ENA
en => temp[7].ENA
en => temp[8].ENA
en => temp[9].ENA
reset => temp[0].ACLR
reset => temp[1].ACLR
reset => temp[2].ACLR
reset => temp[3].ACLR
reset => temp[4].ACLR
reset => temp[5].ACLR
reset => temp[6].ACLR
reset => temp[7].ACLR
reset => temp[8].ACLR
reset => temp[9].ACLR
out1[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
out1[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
out1[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
out1[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE
out1[4] <= temp[4].DB_MAX_OUTPUT_PORT_TYPE
out1[5] <= temp[5].DB_MAX_OUTPUT_PORT_TYPE
out1[6] <= temp[6].DB_MAX_OUTPUT_PORT_TYPE
out1[7] <= temp[7].DB_MAX_OUTPUT_PORT_TYPE
out1[8] <= temp[8].DB_MAX_OUTPUT_PORT_TYPE
out1[9] <= temp[9].DB_MAX_OUTPUT_PORT_TYPE


|DE2_TOP|dds:u1|QQ:b2v_inst1
IN1[0] => OUT[0].DATAIN
IN1[1] => OUT[1].DATAIN
IN1[2] => OUT[2].DATAIN
IN1[3] => OUT[3].DATAIN
IN1[4] => OUT[4].DATAIN
IN1[5] => OUT[5].DATAIN
IN1[6] => OUT[6].DATAIN
IN1[7] => OUT[7].DATAIN
IN1[8] => OUT[8].DATAIN
IN1[9] => OUT[9].DATAIN
IN2[0] => OUT[13].DATAIN
IN2[1] => OUT[14].DATAIN
IN2[2] => OUT[15].DATAIN
IN2[3] => OUT[16].DATAIN
IN2[4] => OUT[17].DATAIN
IN2[5] => OUT[18].DATAIN
IN2[6] => OUT[19].DATAIN
IN2[7] => OUT[20].DATAIN
IN2[8] => OUT[21].DATAIN
IN2[9] => OUT[22].DATAIN
OUT[0] <= IN1[0].DB_MAX_OUTPUT_PORT_TYPE
OUT[1] <= IN1[1].DB_MAX_OUTPUT_PORT_TYPE
OUT[2] <= IN1[2].DB_MAX_OUTPUT_PORT_TYPE
OUT[3] <= IN1[3].DB_MAX_OUTPUT_PORT_TYPE
OUT[4] <= IN1[4].DB_MAX_OUTPUT_PORT_TYPE
OUT[5] <= IN1[5].DB_MAX_OUTPUT_PORT_TYPE
OUT[6] <= IN1[6].DB_MAX_OUTPUT_PORT_TYPE
OUT[7] <= IN1[7].DB_MAX_OUTPUT_PORT_TYPE
OUT[8] <= IN1[8].DB_MAX_OUTPUT_PORT_TYPE
OUT[9] <= IN1[9].DB_MAX_OUTPUT_PORT_TYPE
OUT[10] <= <GND>
OUT[11] <= <GND>
OUT[12] <= <GND>
OUT[13] <= IN2[0].DB_MAX_OUTPUT_PORT_TYPE
OUT[14] <= IN2[1].DB_MAX_OUTPUT_PORT_TYPE
OUT[15] <= IN2[2].DB_MAX_OUTPUT_PORT_TYPE
OUT[16] <= IN2[3].DB_MAX_OUTPUT_PORT_TYPE
OUT[17] <= IN2[4].DB_MAX_OUTPUT_PORT_TYPE
OUT[18] <= IN2[5].DB_MAX_OUTPUT_PORT_TYPE
OUT[19] <= IN2[6].DB_MAX_OUTPUT_PORT_TYPE
OUT[20] <= IN2[7].DB_MAX_OUTPUT_PORT_TYPE
OUT[21] <= IN2[8].DB_MAX_OUTPUT_PORT_TYPE
OUT[22] <= IN2[9].DB_MAX_OUTPUT_PORT_TYPE
OUT[23] <= <GND>
OUT[24] <= <GND>
OUT[25] <= <GND>
OUT[26] <= <GND>
OUT[27] <= <GND>
OUT[28] <= <GND>
OUT[29] <= <GND>
OUT[30] <= <GND>
OUT[31] <= <GND>


|DE2_TOP|dds:u1|reg3:b2v_inst10
clk => dout[0]~reg0.CLK
clk => dout[1]~reg0.CLK
clk => dout[2]~reg0.CLK
clk => dout[3]~reg0.CLK
clk => dout[4]~reg0.CLK
clk => dout[5]~reg0.CLK
clk => dout[6]~reg0.CLK
clk => dout[7]~reg0.CLK
clk => dout[8]~reg0.CLK
clk => dout[9]~reg0.CLK
din[0] => dout[0]~reg0.DATAIN
din[1] => dout[1]~reg0.DATAIN
din[2] => dout[2]~reg0.DATAIN
din[3] => dout[3]~reg0.DATAIN
din[4] => dout[4]~reg0.DATAIN
din[5] => dout[5]~reg0.DATAIN
din[6] => dout[6]~reg0.DATAIN
din[7] => dout[7]~reg0.DATAIN
din[8] => dout[8]~reg0.DATAIN
din[9] => dout[9]~reg0.DATAIN
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_TOP|dds:u1|reg3:b2v_inst11
clk => dout[0]~reg0.CLK
clk => dout[1]~reg0.CLK
clk => dout[2]~reg0.CLK
clk => dout[3]~reg0.CLK
clk => dout[4]~reg0.CLK
clk => dout[5]~reg0.CLK
clk => dout[6]~reg0.CLK
clk => dout[7]~reg0.CLK
clk => dout[8]~reg0.CLK
clk => dout[9]~reg0.CLK
din[0] => dout[0]~reg0.DATAIN
din[1] => dout[1]~reg0.DATAIN
din[2] => dout[2]~reg0.DATAIN
din[3] => dout[3]~reg0.DATAIN
din[4] => dout[4]~reg0.DATAIN
din[5] => dout[5]~reg0.DATAIN
din[6] => dout[6]~reg0.DATAIN
din[7] => dout[7]~reg0.DATAIN
din[8] => dout[8]~reg0.DATAIN
din[9] => dout[9]~reg0.DATAIN
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_TOP|dds:u1|reg1:b2v_inst2
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
d[8] => q[8]~reg0.DATAIN
d[9] => q[9]~reg0.DATAIN
clk => q[0]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[6]~reg0.CLK
clk => q[7]~reg0.CLK
clk => q[8]~reg0.CLK
clk => q[9]~reg0.CLK
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[8] <= q[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[9] <= q[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_TOP|dds:u1|SEG7_LUT_8:b2v_inst3
oSEG0[0] <= SEG7_LUT:u0.port0
oSEG0[1] <= SEG7_LUT:u0.port0
oSEG0[2] <= SEG7_LUT:u0.port0
oSEG0[3] <= SEG7_LUT:u0.port0
oSEG0[4] <= SEG7_LUT:u0.port0
oSEG0[5] <= SEG7_LUT:u0.port0
oSEG0[6] <= SEG7_LUT:u0.port0
oSEG1[0] <= SEG7_LUT:u1.port0
oSEG1[1] <= SEG7_LUT:u1.port0
oSEG1[2] <= SEG7_LUT:u1.port0
oSEG1[3] <= SEG7_LUT:u1.port0
oSEG1[4] <= SEG7_LUT:u1.port0
oSEG1[5] <= SEG7_LUT:u1.port0
oSEG1[6] <= SEG7_LUT:u1.port0
oSEG2[0] <= SEG7_LUT:u2.port0
oSEG2[1] <= SEG7_LUT:u2.port0
oSEG2[2] <= SEG7_LUT:u2.port0
oSEG2[3] <= SEG7_LUT:u2.port0
oSEG2[4] <= SEG7_LUT:u2.port0
oSEG2[5] <= SEG7_LUT:u2.port0
oSEG2[6] <= SEG7_LUT:u2.port0
oSEG3[0] <= SEG7_LUT:u3.port0
oSEG3[1] <= SEG7_LUT:u3.port0
oSEG3[2] <= SEG7_LUT:u3.port0
oSEG3[3] <= SEG7_LUT:u3.port0
oSEG3[4] <= SEG7_LUT:u3.port0
oSEG3[5] <= SEG7_LUT:u3.port0
oSEG3[6] <= SEG7_LUT:u3.port0
oSEG4[0] <= SEG7_LUT:u4.port0
oSEG4[1] <= SEG7_LUT:u4.port0
oSEG4[2] <= SEG7_LUT:u4.port0
oSEG4[3] <= SEG7_LUT:u4.port0
oSEG4[4] <= SEG7_LUT:u4.port0
oSEG4[5] <= SEG7_LUT:u4.port0
oSEG4[6] <= SEG7_LUT:u4.port0
oSEG5[0] <= SEG7_LUT:u5.port0
oSEG5[1] <= SEG7_LUT:u5.port0
oSEG5[2] <= SEG7_LUT:u5.port0
oSEG5[3] <= SEG7_LUT:u5.port0
oSEG5[4] <= SEG7_LUT:u5.port0
oSEG5[5] <= SEG7_LUT:u5.port0
oSEG5[6] <= SEG7_LUT:u5.port0
oSEG6[0] <= SEG7_LUT:u6.port0
oSEG6[1] <= SEG7_LUT:u6.port0
oSEG6[2] <= SEG7_LUT:u6.port0
oSEG6[3] <= SEG7_LUT:u6.port0
oSEG6[4] <= SEG7_LUT:u6.port0
oSEG6[5] <= SEG7_LUT:u6.port0
oSEG6[6] <= SEG7_LUT:u6.port0
oSEG7[0] <= SEG7_LUT:u7.port0
oSEG7[1] <= SEG7_LUT:u7.port0
oSEG7[2] <= SEG7_LUT:u7.port0
oSEG7[3] <= SEG7_LUT:u7.port0
oSEG7[4] <= SEG7_LUT:u7.port0
oSEG7[5] <= SEG7_LUT:u7.port0
oSEG7[6] <= SEG7_LUT:u7.port0
iDIG[0] => iDIG[0]~31.IN1
iDIG[1] => iDIG[1]~30.IN1
iDIG[2] => iDIG[2]~29.IN1
iDIG[3] => iDIG[3]~28.IN1
iDIG[4] => iDIG[4]~27.IN1
iDIG[5] => iDIG[5]~26.IN1
iDIG[6] => iDIG[6]~25.IN1
iDIG[7] => iDIG[7]~24.IN1
iDIG[8] => iDIG[8]~23.IN1
iDIG[9] => iDIG[9]~22.IN1
iDIG[10] => iDIG[10]~21.IN1
iDIG[11] => iDIG[11]~20.IN1
iDIG[12] => iDIG[12]~19.IN1
iDIG[13] => iDIG[13]~18.IN1