de2_top.hif

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

Version 6.0 Build 178 04/27/2006 SJ Full Version
11
767
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
dds
# storage
db|DE2_TOP.(1).cnf
db|DE2_TOP.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds.v
d67ff12317f54e594a65ba31e24a59
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1
}
# end
# entity
sum99
# storage
db|DE2_TOP.(2).cnf
db|DE2_TOP.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sum99.vhd
5e5274a52b6b2a28af8cbff19232
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|sum99:b2v_inst
}
# end
# entity
QQ
# storage
db|DE2_TOP.(3).cnf
db|DE2_TOP.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
QQ.v
90d1a0d75699898e4d387eafa8f3bd3
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|QQ:b2v_inst1
}
# end
# entity
reg3
# storage
db|DE2_TOP.(4).cnf
db|DE2_TOP.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg3.vhd
7155c53b2688fa73485866fbfee60
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|reg3:b2v_inst10
dds:u1|reg3:b2v_inst11
}
# end
# entity
reg1
# storage
db|DE2_TOP.(5).cnf
db|DE2_TOP.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg1.vhd
524af60c479a9c8f3f3a761e7a7577
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|reg1:b2v_inst2
}
# end
# entity
SEG7_LUT_8
# storage
db|DE2_TOP.(6).cnf
db|DE2_TOP.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT_8.v
a1b23bbdc3c12f4d7d6d807db83dd463
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|SEG7_LUT_8:b2v_inst3
}
# end
# entity
SEG7_LUT
# storage
db|DE2_TOP.(7).cnf
db|DE2_TOP.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT.v
3b3d255e288f865668e6d661da57411
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u0
dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u1
dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u2
dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u3
dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u4
dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u5
dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u6
dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u7
}
# end
# entity
reg2
# storage
db|DE2_TOP.(8).cnf
db|DE2_TOP.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg2.vhd
5d8d6be41e9ff13ee30f7448c7ba
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|reg2:b2v_inst4
}
# end
# entity
adder
# storage
db|DE2_TOP.(9).cnf
db|DE2_TOP.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
adder.vhd
ba13fde44a37ff68a4f5a4e629880f6
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|adder:b2v_inst5
}
# end
# entity
sinrom
# storage
db|DE2_TOP.(10).cnf
db|DE2_TOP.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
sinrom.vhd
8aeb2a3178c02e2044f65f628033e467
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
dds:u1|sinrom:b2v_inst8
dds:u1|sinrom:b2v_inst9
}
# end
# entity
altsyncram
# storage
db|DE2_TOP.(11).cnf
db|DE2_TOP.(11).cnf
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
sin_rom.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_71a1
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
c:|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
c:|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
c:|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
c:|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
}
# hierarchies {
dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component
dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_71a1
# storage
db|DE2_TOP.(12).cnf
db|DE2_TOP.(12).cnf
# case_insensitive
# source_file
db|altsyncram_71a1.tdf
d449b9569bc5ef7129818ddd67e473d
6
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated
dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated
}
# end
# entity
altsyncram_rsf2
# storage
db|DE2_TOP.(13).cnf
db|DE2_TOP.(13).cnf
# case_insensitive
# source_file
db|altsyncram_rsf2.tdf
75aa3f7d4b128da4ca1b5a61563a182
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b1
-1
3
data_b0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sin_rom.mif
823d66eaa93374a028fc4e1ed3c21a5e
}
# hierarchies {
dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1
dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1
}
# end
# entity
sld_mod_ram_rom
# storage
db|DE2_TOP.(14).cnf
db|DE2_TOP.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|sld_mod_ram_rom.vhd
cace3e25a569423fe6146c8930ac7b
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_node_info
135818752
PARAMETER_DEC
DEF
sld_ip_version
1
PARAMETER_DEC
DEF
sld_ip_minor_version
2
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
width_word
10
PARAMETER_UNKNOWN
USR
numwords
1024
PARAMETER_UNKNOWN
USR
widthad
10
PARAMETER_UNKNOWN
USR
shift_count_bits
4
PARAMETER_UNKNOWN
USR
cvalue
0000000000
PARAMETER_UNKNOWN
USR
is_data_in_ram
1
PARAMETER_UNKNOWN
USR
is_readable
1
PARAMETER_UNKNOWN
USR
node_name
1919905073
PARAMETER_UNKNOWN
USR
}
# hierarchies {
dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2
dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2
}
# end
# entity
sld_rom_sr
# storage
db|DE2_TOP.(15).cnf
db|DE2_TOP.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|sld_rom_sr.vhd
e685b197d41e27ef5fe9d8f6d2755ee3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
80
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
 constraint(rom_data)
79 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
}
# end
# entity
sld_signaltap
# storage
db|DE2_TOP.(16).cnf
db|DE2_TOP.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|sld_signaltap.vhd
bafecb7d1122d6345cc8e1bd9a2a4bb5
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
536899072
PARAMETER_UNKNOWN
USR
sld_ip_version
4
PARAMETER_DEC
DEF
sld_ip_minor_version
0
PARAMETER_DEC
DEF
sld_common_ip_version
0
PARAMETER_DEC
DEF
sld_data_bits
107
PARAMETER_UNKNOWN
USR
sld_trigger_bits
107
PARAMETER_UNKNOWN
USR
sld_data_bit_cntr_bits
7
PARAMETER_UNKNOWN
USR
sld_node_crc_bits
32
PARAMETER_DEC
DEF
sld_node_crc_hiword
62559
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
1877
PARAMETER_UNKNOWN
USR
sld_incremental_routing
0
PARAMETER_DEC
DEF
sld_sample_depth
2048
PARAMETER_UNKNOWN
USR
sld_mem_address_bits
11
PARAMETER_UNKNOWN
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
1
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_2
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_3
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_4
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_5
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_6
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_7
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_8
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_9
NONE
PARAMETER_STRING
DEF
sld_advanced_trigger_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
341
PARAMETER_UNKNOWN
USR
sld_inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
}
# end
# entity
sld_ela_control
# storage
db|DE2_TOP.(17).cnf
db|DE2_TOP.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|sld_ela_control.vhd
50f992f5a51ab387a478321569ab2eee
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
4
PARAMETER_DEC
USR
ip_minor_version
0
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_input_width
107
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
trigger_in_enabled
1
PARAMETER_DEC
USR
enable_clk_edge_def
0
PARAMETER_DEC
USR
enable_async_glitch
0
PARAMETER_DEC
USR
enable_sync_normal
1
PARAMETER_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_DEC
USR
trigger_level_pipeline
1
PARAMETER_DEC
USR
ela_status_bits
4
PARAMETER_DEC
USR
mem_address_bits
11
PARAMETER_DEC
USR
sample_depth
2048
PARAMETER_DEC
USR
inversion_mask_length
341
PARAMETER_DEC
USR
inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_BIN
USR
power_up_trigger
0
PARAMETER_DEC
USR
 constraint(acq_trigger_in)
106 downto 0
PARAMETER_STRING
USR
 constraint(status)
3 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_shiftreg
# storage
db|DE2_TOP.(18).cnf
db|DE2_TOP.(18).cnf
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|lpm_shiftreg.tdf
5c3a6ccfa9758137252ac34dcc2420
6
# user_parameter {
LPM_WIDTH
20
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
load
-1
1
data9
-1
1
data8
-1
1
data7
-1
1
data6
-1
1
data5
-1
1
data4
-1
1
data3
-1
1
data2
-1
1
data19
-1
1
data18
-1
1
data17
-1
1
data16
-1
1
data15
-1
1
data14
-1
1
data13
-1
1
data12
-1
1
data11
-1
1
data10
-1
1
data1
-1
1
data0
-1
1
}
# include_file {
c:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
c:|altera|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
c:|altera|quartus60|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
}
# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|DE2_TOP.(19).cnf
db|DE2_TOP.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|sld_ela_control.vhd
50f992f5a51ab387a478321569ab2eee
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
4
PARAMETER_DEC
USR
ip_minor_version
0
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
trigger_level
1
PARAMETER_DEC
USR
data_bits
107
PARAMETER_DEC
USR
async_enabled
0
PARAMETER_DEC
USR
sync_enabled
1
PARAMETER_DEC
USR
pipeline
1
PARAMETER_DEC
USR
inversion_mask_length
341
PARAMETER_DEC
USR
inversion_mask
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_BIN
USR
power_up_trigger
0
PARAMETER_DEC
USR
 constraint(data_in)
106 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_ena)
0 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_shiftreg
# storage
db|DE2_TOP.(20).cnf
db|DE2_TOP.(20).cnf
# case_insensitive
# source_file
c:|altera|quartus60|libraries|megafunctions|lpm_shiftreg.tdf
5c3a6ccfa9758137252ac34dcc2420
6
# user_parameter {
LPM_WIDTH
321
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftout
-1
3
shiftin
-1
3
q99
-1
3
q98
-1
3
q97
-1
3
q96
-1
3
q95
-1
3
q94
-1
3
q93
-1
3
q92
-1
3
q91
-1
3
q90
-1
3
q9
-1
3
q89
-1