de2_top.map.qmsg

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

{ "Warning" "WSGN_SEARCH_FILE" "QQ.v 1 1 " "Warning: Using design file QQ.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 QQ " "Info: Found entity 1: QQ" {  } { { "QQ.v" "" { Text "F:/dds/dds/DE2_Top/QQ.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "QQ dds:u1\|QQ:b2v_inst1 " "Info: Elaborating entity \"QQ\" for hierarchy \"dds:u1\|QQ:b2v_inst1\"" {  } { { "dds.v" "b2v_inst1" { Text "F:/dds/dds/DE2_Top/dds.v" 63 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "42 32 QQ.v(6) " "Warning (10230): Verilog HDL assignment warning at QQ.v(6): truncated value with size 42 to match size of target (32)" {  } { { "QQ.v" "" { Text "F:/dds/dds/DE2_Top/QQ.v" 6 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "reg3.vhd 2 1 " "Warning: Using design file reg3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg3-behav " "Info: Found design unit 1: reg3-behav" {  } { { "reg3.vhd" "" { Text "F:/dds/dds/DE2_Top/reg3.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg3 " "Info: Found entity 1: reg3" {  } { { "reg3.vhd" "" { Text "F:/dds/dds/DE2_Top/reg3.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg3 dds:u1\|reg3:b2v_inst10 " "Info: Elaborating entity \"reg3\" for hierarchy \"dds:u1\|reg3:b2v_inst10\"" {  } { { "dds.v" "b2v_inst10" { Text "F:/dds/dds/DE2_Top/dds.v" 66 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "reg1.vhd 2 1 " "Warning: Using design file reg1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg1-art " "Info: Found design unit 1: reg1-art" {  } { { "reg1.vhd" "" { Text "F:/dds/dds/DE2_Top/reg1.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg1 " "Info: Found entity 1: reg1" {  } { { "reg1.vhd" "" { Text "F:/dds/dds/DE2_Top/reg1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg1 dds:u1\|reg1:b2v_inst2 " "Info: Elaborating entity \"reg1\" for hierarchy \"dds:u1\|reg1:b2v_inst2\"" {  } { { "dds.v" "b2v_inst2" { Text "F:/dds/dds/DE2_Top/dds.v" 72 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SEG7_LUT_8.v 1 1 " "Warning: Using design file SEG7_LUT_8.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Info: Found entity 1: SEG7_LUT_8" {  } { { "SEG7_LUT_8.v" "" { Text "F:/dds/dds/DE2_Top/SEG7_LUT_8.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 dds:u1\|SEG7_LUT_8:b2v_inst3 " "Info: Elaborating entity \"SEG7_LUT_8\" for hierarchy \"dds:u1\|SEG7_LUT_8:b2v_inst3\"" {  } { { "dds.v" "b2v_inst3" { Text "F:/dds/dds/DE2_Top/dds.v" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "SEG7_LUT.v 1 1 " "Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" {  } { { "SEG7_LUT.v" "" { Text "F:/dds/dds/DE2_Top/SEG7_LUT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT dds:u1\|SEG7_LUT_8:b2v_inst3\|SEG7_LUT:u0 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"dds:u1\|SEG7_LUT_8:b2v_inst3\|SEG7_LUT:u0\"" {  } { { "SEG7_LUT_8.v" "u0" { Text "F:/dds/dds/DE2_Top/SEG7_LUT_8.v" 5 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "reg2.vhd 2 1 " "Warning: Using design file reg2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg2-art " "Info: Found design unit 1: reg2-art" {  } { { "reg2.vhd" "" { Text "F:/dds/dds/DE2_Top/reg2.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg2 " "Info: Found entity 1: reg2" {  } { { "reg2.vhd" "" { Text "F:/dds/dds/DE2_Top/reg2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg2 dds:u1\|reg2:b2v_inst4 " "Info: Elaborating entity \"reg2\" for hierarchy \"dds:u1\|reg2:b2v_inst4\"" {  } { { "dds.v" "b2v_inst4" { Text "F:/dds/dds/DE2_Top/dds.v" 78 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder dds:u1\|adder:b2v_inst5 " "Info: Elaborating entity \"adder\" for hierarchy \"dds:u1\|adder:b2v_inst5\"" {  } { { "dds.v" "b2v_inst5" { Text "F:/dds/dds/DE2_Top/dds.v" 81 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sinrom dds:u1\|sinrom:b2v_inst8 " "Info: Elaborating entity \"sinrom\" for hierarchy \"dds:u1\|sinrom:b2v_inst8\"" {  } { { "dds.v" "b2v_inst8" { Text "F:/dds/dds/DE2_Top/dds.v" 84 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\"" {  } { { "sinrom.vhd" "altsyncram_component" { Text "F:/dds/dds/DE2_Top/sinrom.vhd" 81 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\"" {  } { { "sinrom.vhd" "" { Text "F:/dds/dds/DE2_Top/sinrom.vhd" 81 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_71a1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_71a1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_71a1 " "Info: Found entity 1: altsyncram_71a1" {  } { { "db/altsyncram_71a1.tdf" "" { Text "F:/dds/dds/DE2_Top/db/altsyncram_71a1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_71a1 dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated " "Info: Elaborating entity \"altsyncram_71a1\" for hierarchy \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rsf2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rsf2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rsf2 " "Info: Found entity 1: altsyncram_rsf2" {  } { { "db/altsyncram_rsf2.tdf" "" { Text "F:/dds/dds/DE2_Top/db/altsyncram_rsf2.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_rsf2 dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|altsyncram_rsf2:altsyncram1 " "Info: Elaborating entity \"altsyncram_rsf2\" for hierarchy \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|altsyncram_rsf2:altsyncram1\"" {  } { { "db/altsyncram_71a1.tdf" "altsyncram1" { Text "F:/dds/dds/DE2_Top/db/altsyncram_71a1.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_71a1.tdf" "mgl_prim2" { Text "F:/dds/dds/DE2_Top/db/altsyncram_71a1.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_71a1.tdf" "" { Text "F:/dds/dds/DE2_Top/db/altsyncram_71a1.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\", which is child of megafunction instantiation \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } } { "db/altsyncram_71a1.tdf" "" { Text "F:/dds/dds/DE2_Top/db/altsyncram_71a1.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Instantiated megafunction \"dds:u1\|sinrom:b2v_inst8\|altsyncram:altsyncram_component\|altsyncram_71a1:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 0000000000 " "Info: Parameter \"CVALUE\" = \"0000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Info: Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Info: Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 1919905073 " "Info: Parameter \"NODE_NAME\" = \"1919905073\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 1024 " "Info: Parameter \"NUMWORDS\" = \"1024\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 4 " "Info: Parameter \"SHIFT_COUNT_BITS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 10 " "Info: Parameter \"WIDTH_WORD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 10 " "Info: Parameter \"WIDTHAD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "db/altsyncram_71a1.tdf" "" { Text "F:/dds/dds/DE2_Top/db/altsyncram_71a1.tdf" 35 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "en u1 32 1 " "Warning: Port \"en\" on the entity instantiation of \"u1\" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be driven by GND." {  } { { "DE2_TOP.v" "u1" { Text "F:/dds/dds/DE2_Top/DE2_TOP.v" 358 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "k u1 1 10 " "Warning: Port \"k\" on the entity instantiation of \"u1\" is connected to a signal of width 1. The formal width of the signal in the module is 10.  Extra bits will be driven by GND." {  } { { "DE2_TOP.v" "u1" { Text "F:/dds/dds/DE2_Top/DE2_TOP.v" 358 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "p u1 8 10 " "Warning: Port \"p\" on the entity instantiation of \"u1\" is connected to a signal of width 8. The formal width of the signal in the module is 10.  Extra bits will be driven by GND." {  } { { "DE2_TOP.v" "u1" { Text "F:/dds/dds/DE2_Top/DE2_TOP.v" 358 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "reset u1 32 1 " "Warning: Port \"reset\" on the entity instantiation of \"u1\" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be driven by GND." {  } { { "DE2_TOP.v" "u1" { Text "F:/dds/dds/DE2_Top/DE2_TOP.v" 358 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Error" "ESGN_NO_INCR_TAP_IN_REGULAR_SYNTH" "" "Error: Incremental instances created by tools that communicate with a device via the JTAG interface, such as SignalTap II Logic Analyzer, can only be supported when incremental compilation is set to Full incremental compilation" {  } {  } 0 0 "Incremental instances created by tools that communicate with a device via the JTAG interface, such as SignalTap II Logic Analyzer, can only be supported when incremental compilation is set to Full incremental compilation" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  147 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 147 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Jul 24 15:43:45 2007 " "Error: Processing ended: Tue Jul 24 15:43:45 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Error: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/dds/dds/DE2_Top/D