dds.vhd

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds is
port(k: in std_logic_vector(9 downto 0);
     en: in std_logic;
     reset: in std_logic;
      clk : in std_logic;
     q :   out std_logic_vector(8 downto 0) );
end entity dds;
architecture art of dds is 
component sum99 is 
  port( k: in std_logic_vector(9 downto 0);
        en : in std_logic;
        reset: in std_logic;
        clk : in std_logic;
        out1 : out std_logic_vector(9 downto 0) );
end component sum99;
component reg1 is
  port ( d: in std_logic_vector(9 downto 0);
     clk : in std_logic;
     q: out std_logic_vector(9 downto 0) );
end component reg1;
component rom is
  port (clk : in std_logic;
        addr : in std_logic_vector( 9 downto 0);
        outp : out std_logic_vector(8 downto 0));
end component rom;
component reg2 is
   port (d : in std_logic_vector(9 downto 0);
         clk: in std_logic;
          q : out std_logic_vector(9 downto 0));
end component reg2; 
signal s1 : std_logic_vector(9 downto 0);
signal s2 : std_logic_vector(9 downto 0);
signal s3 : std_logic_vector(8 downto 0);
begin
u0 : sum99 port map(k=>k,en=>en,reset=>reset,clk=>clk,out1=>s1);
u1 : reg1 port map(d=>s1,clk=>clk,q=>s2);
u2 : rom port map(addr=>s2,clk=>clk,outp=>s3);
u3 : reg2 port map(d=>s3,clk=>clk,q=>q);
end architecture art;