stp1.stp

来自「一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计」· STP 代码 · 共 512 行 · 第 1/5 页

          <wire connection_status="true" name="dds:u1|reg3:b2v_inst11|dout[8]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|reg3:b2v_inst11|dout[9]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[8]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst8|address[9]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[8]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="dds:u1|sinrom:b2v_inst9|address[9]" tap_mode="classic" type="combinatorial"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="HEX0" order="msb_to_lsb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="HEX0[6]"/>
            <net is_signal_inverted="no" name="HEX0[5]"/>
            <net is_signal_inverted="no" name="HEX0[4]"/>
            <net is_signal_inverted="no" name="HEX0[3]"/>
            <net is_signal_inverted="no" name="HEX0[2]"/>
            <net is_signal_inverted="no" name="HEX0[1]"/>
            <net is_signal_inverted="no" name="HEX0[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="HEX1" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="HEX1[6]"/>
            <net is_signal_inverted="no" name="HEX1[5]"/>
            <net is_signal_inverted="no" name="HEX1[4]"/>
            <net is_signal_inverted="no" name="HEX1[3]"/>
            <net is_signal_inverted="no" name="HEX1[2]"/>
            <net is_signal_inverted="no" name="HEX1[1]"/>
            <net is_signal_inverted="no" name="HEX1[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="HEX2" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="HEX2[6]"/>
            <net is_signal_inverted="no" name="HEX2[5]"/>
            <net is_signal_inverted="no" name="HEX2[4]"/>
            <net is_signal_inverted="no" name="HEX2[3]"/>
            <net is_signal_inverted="no" name="HEX2[2]"/>
            <net is_signal_inverted="no" name="HEX2[1]"/>
            <net is_signal_inverted="no" name="HEX2[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="HEX3" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="HEX3[6]"/>
            <net is_signal_inverted="no" name="HEX3[5]"/>
            <net is_signal_inverted="no" name="HEX3[4]"/>
            <net is_signal_inverted="no" name="HEX3[3]"/>
            <net is_signal_inverted="no" name="HEX3[2]"/>
            <net is_signal_inverted="no" name="HEX3[1]"/>
            <net is_signal_inverted="no" name="HEX3[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="HEX4" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="HEX4[6]"/>
            <net is_signal_inverted="no" name="HEX4[5]"/>
            <net is_signal_inverted="no" name="HEX4[4]"/>
            <net is_signal_inverted="no" name="HEX4[3]"/>
            <net is_signal_inverted="no" name="HEX4[2]"/>
            <net is_signal_inverted="no" name="HEX4[1]"/>
            <net is_signal_inverted="no" name="HEX4[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="HEX5" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="HEX5[6]"/>
            <net is_signal_inverted="no" name="HEX5[5]"/>
            <net is_signal_inverted="no" name="HEX5[4]"/>
            <net is_signal_inverted="no" name="HEX5[3]"/>
            <net is_signal_inverted="no" name="HEX5[2]"/>
            <net is_signal_inverted="no" name="HEX5[1]"/>
            <net is_signal_inverted="no" name="HEX5[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="HEX6" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="HEX6[6]"/>
            <net is_signal_inverted="no" name="HEX6[5]"/>
            <net is_signal_inverted="no" name="HEX6[4]"/>
            <net is_signal_inverted="no" name="HEX6[3]"/>
            <net is_signal_inverted="no" name="HEX6[2]"/>
            <net is_signal_inverted="no" name="HEX6[1]"/>
            <net is_signal_inverted="no" name="HEX6[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="HEX7" order="msb_to_lsb" radix="hex" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="HEX7[6]"/>
            <net is_signal_inverted="no" name="HEX7[5]"/>
            <net is_signal_inverted="no" name="HEX7[4]"/>
            <net is_signal_inverted="no" name="HEX7[3]"/>
            <net is_signal_inverted="no" name="HEX7[2]"/>
            <net is_signal_inverted="no" name="HEX7[1]"/>
            <net is_signal_inverted="no" name="HEX7[0]"/>
          </bus>
          <net is_signal_inverted="no" name="KEY[1]"/>
          <bus is_signal_inverted="no" link="all" name="dds:u1|reg3:b2v_inst11|dout" order="msb_to_lsb" radix="line" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="dds:u1|reg3:b2v_inst11|dout[9]"/>
            <net is_signal_inverted="no" name="dds:u1|reg3:b2v_inst11|dout[8]"/>
            <net is_signal_inverted="no" name="dds:u1|reg3:b2v_inst11|dout[7]"/>