reg3.vhd

来自「一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all;
entity reg3 is
  port( clk : in std_logic;
        din : in std_logic_vector(9 downto 0);
        dout : out std_logic_vector(9 downto 0));
end reg3;
architecture behav of reg3 is
begin 
  process(clk,din)
 begin 
  if clk'event and clk ='1' then dout <= din;
  end if;
 end process;
end behav;