adder.vhd

来自「一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
   port(a,b : in std_logic_vector(9 downto 0);
         clk: in std_logic;
         s : out std_logic_vector(9 downto 0));
end adder;
architecture behav of adder is
 --SIGNAL TEMP: std_logic_vector(10 downto 0);
   begin
  process(clk)
   begin
  if clk'EVENT AND CLK='1' then
    s<=a+b;
  end if;
 end process;
end behav;