de2_top.fit.rpt

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

; Total logic elements               ; 1,288 / 33,216 ( 4 % )                   ;
; Total registers                    ; 1110                                     ;
; Total pins                         ; 429 / 475 ( 90 % )                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 239,616 / 483,840 ( 50 % )               ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 0 / 4 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                  ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Option                                         ; Setting                        ; Default Value                  ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Device                                         ; EP2C35F672C6                   ;                                ;
; Use smart compilation                          ; Off                            ; Off                            ;
; Router Timing Optimization Level               ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                    ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                       ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                           ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                    ; Off                            ; Off                            ;
; PowerPlay Power Optimization                   ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing     ; On                             ; On                             ;
; Limit to One Fitting Attempt                   ; Off                            ; Off                            ;
; Final Placement Optimizations                  ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations    ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                  ; 1                              ; 1                              ;
; PCI I/O                                        ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                          ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                      ; Off                            ; Off                            ;
; Auto Global Memory Control Signals             ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II ; Auto                           ; Auto                           ;
; Auto Delay Chains                              ; On                             ; On                             ;
; Auto Merge PLLs                                ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs              ; Off                            ; Off                            ;
; Fitter Effort                                  ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                ; Normal                         ; Normal                         ;
; Auto Global Clock                              ; On                             ; On                             ;
; Auto Global Register Control Signals           ; On                             ; On                             ;
; Always Enable Input Buffers                    ; Off                            ; Off                            ;
+------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                         ;
+--------------------------------+-----------------+------------------+---------------------+-----------+---------------------------------------------------------------------------------------------------------------------------+------------------+
; Node                           ; Action          ; Operation        ; Reason              ; Node Port ; Destination Node                                                                                                          ; Destination Port ;
+--------------------------------+-----------------+------------------+---------------------+-----------+---------------------------------------------------------------------------------------------------------------------------+------------------+
; dds:u1|reg3:b2v_inst10|dout[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[0] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[1] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[2] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[3] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[4] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[5] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[6] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[7] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[8] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst10|dout[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[9] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[0] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[1] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[2] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[3] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[4] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[5] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[6] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[7] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[8] ; PORTADATAOUT     ;
; dds:u1|reg3:b2v_inst11|dout[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|q_a[9] ; PORTADATAOUT     ;
+--------------------------------+-----------------+------------------+---------------------+-----------+---------------------------------------------------------------------------------------------------------------------------+------------------+