de2_top.tan.rpt

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50                     ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK_50'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                              ; To                                                                                                                                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_we_reg         ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_datain_reg0    ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.643 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg0   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg1   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg2   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg3   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg4   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg5   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg6   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg7   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg8   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg9   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_address_reg10  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.659 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_datain_reg1    ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.643 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a83~portb_we_reg         ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.603 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a83~portb_datain_reg0    ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.587 ns                ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.134 ns )      ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a83~portb_address_reg0   ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 5.603 ns                ;