de2_top.tan.rpt

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                                    ; From                                                                                                                                                                              ; To                                                                                                                                                                        ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 4.133 ns                                       ; KEY[1]                                                                                                                                                                            ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[56]                                                                                                                     ; --                           ; CLOCK_50                     ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 11.621 ns                                      ; dds:u1|reg3:b2v_inst10|dout[6]                                                                                                                                                    ; HEX1[0]                                                                                                                                                                   ; CLOCK_50                     ; --                           ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.612 ns                                       ; altera_internal_jtag~TDO                                                                                                                                                          ; altera_reserved_tdo                                                                                                                                                       ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 1.799 ns                                       ; altera_internal_jtag~TMSUTAP                                                                                                                                                      ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]                                                                                                   ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]                                                                                                                                     ; dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|ram_block3a6~portb_we_reg                              ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLOCK_50'                     ; N/A   ; None          ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_datain_reg1 ; CLOCK_50                     ; CLOCK_50                     ; 0            ;
; Total number of failed paths                ;       ;               ;                                                ;                                                                                                                                                                                   ;                                                                                                                                                                           ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;