dds.v

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module dds(
	clk,
	en,
	reset,
	k,
	p,
	hex0,
	hex1,
	hex2,
	hex3,
	hex4,
	hex5,
	hex6,
	hex7
);

input	clk;
input	en;
input	reset;
input	[9:0] k;
input	[9:0] p;
output	[6:0] hex0;
output	[6:0] hex1;
output	[6:0] hex2;
output	[6:0] hex3;
output	[6:0] hex4;
output	[6:0] hex5;
output	[6:0] hex6;
output	[6:0] hex7;

wire	[9:0] POUT;
wire	[9:0] q;
wire	[9:0] SYNTHESIZED_WIRE_0;
wire	[9:0] SYNTHESIZED_WIRE_1;
wire	[9:0] SYNTHESIZED_WIRE_2;
wire	[31:0] SYNTHESIZED_WIRE_3;
wire	[9:0] SYNTHESIZED_WIRE_4;
wire	[9:0] SYNTHESIZED_WIRE_8;
wire	[9:0] SYNTHESIZED_WIRE_6;





sum99	b2v_inst(.clk(clk),
.en(en),.reset(reset),.k(k),.out1(SYNTHESIZED_WIRE_2));

QQ	b2v_inst1(.IN1(q),
.IN2(POUT),.OUT(SYNTHESIZED_WIRE_3));

reg3	b2v_inst10(.clk(clk),
.din(SYNTHESIZED_WIRE_0),.dout(q));

reg3	b2v_inst11(.clk(clk),
.din(SYNTHESIZED_WIRE_1),.dout(POUT));

reg1	b2v_inst2(.clk(clk),
.d(SYNTHESIZED_WIRE_2),.q(SYNTHESIZED_WIRE_8));

SEG7_LUT_8	b2v_inst3(.iDIG(SYNTHESIZED_WIRE_3),
.oSEG0(hex0),.oSEG1(hex1),.oSEG2(hex2),.oSEG3(hex3),.oSEG4(hex4),.oSEG5(hex5),.oSEG6(hex6),.oSEG7(hex7));

reg2	b2v_inst4(.clk(clk),
.d(SYNTHESIZED_WIRE_4),.q(SYNTHESIZED_WIRE_6));

adder	b2v_inst5(.a(p),.clk(clk),
.b(SYNTHESIZED_WIRE_8),.s(SYNTHESIZED_WIRE_4));

sinrom	b2v_inst8(.inclock(clk),
.address(SYNTHESIZED_WIRE_6),.q(SYNTHESIZED_WIRE_0));

sinrom	b2v_inst9(.inclock(clk),
.address(SYNTHESIZED_WIRE_8),.q(SYNTHESIZED_WIRE_1));


endmodule