de2_top.tan.summary

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.133 ns
From           : KEY[1]
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[56]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.621 ns
From           : dds:u1|reg3:b2v_inst10|dout[6]
To             : HEX1[0]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.612 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.799 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 163.03 MHz ( period = 6.134 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
To             : dds:u1|sinrom:b2v_inst9|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1|ram_block3a6~portb_we_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 163.03 MHz ( period = 6.134 ns )
From           : sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_9oh:auto_generated|safe_q[0]
To             : sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_31j2:auto_generated|altsyncram_e7l1:altsyncram1|ram_block2a74~portb_datain_reg1
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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