de2_top.map.rpt

一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计的好东西!

Warning (10034): Output port "SRAM_ADDR[2]" at DE2_TOP.v(222) has no driver
Warning (10034): Output port "SRAM_ADDR[1]" at DE2_TOP.v(222) has no driver
Warning (10034): Output port "SRAM_ADDR[0]" at DE2_TOP.v(222) has no driver
Warning (10034): Output port "SRAM_UB_N" at DE2_TOP.v(223) has no driver
Warning (10034): Output port "SRAM_LB_N" at DE2_TOP.v(224) has no driver
Warning (10034): Output port "SRAM_WE_N" at DE2_TOP.v(225) has no driver
Warning (10034): Output port "SRAM_CE_N" at DE2_TOP.v(226) has no driver
Warning (10034): Output port "SRAM_OE_N" at DE2_TOP.v(227) has no driver
Warning (10034): Output port "OTG_ADDR[1]" at DE2_TOP.v(230) has no driver
Warning (10034): Output port "OTG_ADDR[0]" at DE2_TOP.v(230) has no driver
Warning (10034): Output port "OTG_CS_N" at DE2_TOP.v(231) has no driver
Warning (10034): Output port "OTG_RD_N" at DE2_TOP.v(232) has no driver
Warning (10034): Output port "OTG_WR_N" at DE2_TOP.v(233) has no driver
Warning (10034): Output port "OTG_RST_N" at DE2_TOP.v(234) has no driver
Warning (10034): Output port "OTG_FSPEED" at DE2_TOP.v(235) has no driver
Warning (10034): Output port "OTG_LSPEED" at DE2_TOP.v(236) has no driver
Warning (10034): Output port "OTG_DACK0_N" at DE2_TOP.v(241) has no driver
Warning (10034): Output port "OTG_DACK1_N" at DE2_TOP.v(242) has no driver
Warning (10034): Output port "LCD_RW" at DE2_TOP.v(247) has no driver
Warning (10034): Output port "LCD_EN" at DE2_TOP.v(248) has no driver
Warning (10034): Output port "LCD_RS" at DE2_TOP.v(249) has no driver
Warning (10034): Output port "SD_CLK" at DE2_TOP.v(254) has no driver
Warning (10034): Output port "I2C_SCLK" at DE2_TOP.v(257) has no driver
Warning (10034): Output port "TDO" at DE2_TOP.v(265) has no driver
Warning (10034): Output port "VGA_CLK" at DE2_TOP.v(267) has no driver
Warning (10034): Output port "VGA_HS" at DE2_TOP.v(268) has no driver
Warning (10034): Output port "VGA_VS" at DE2_TOP.v(269) has no driver
Warning (10034): Output port "VGA_BLANK" at DE2_TOP.v(270) has no driver
Warning (10034): Output port "VGA_SYNC" at DE2_TOP.v(271) has no driver
Warning (10034): Output port "VGA_R[9]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[8]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[7]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[6]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[5]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[4]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[3]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[2]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[1]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_R[0]" at DE2_TOP.v(272) has no driver
Warning (10034): Output port "VGA_G[9]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[8]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[7]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[6]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[5]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[4]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[3]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[2]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[1]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_G[0]" at DE2_TOP.v(273) has no driver
Warning (10034): Output port "VGA_B[9]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[8]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[7]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[6]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[5]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[4]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[3]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[2]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[1]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "VGA_B[0]" at DE2_TOP.v(274) has no driver
Warning (10034): Output port "ENET_CMD" at DE2_TOP.v(277) has no driver
Warning (10034): Output port "ENET_CS_N" at DE2_TOP.v(278) has no driver
Warning (10034): Output port "ENET_WR_N" at DE2_TOP.v(279) has no driver
Warning (10034): Output port "ENET_RD_N" at DE2_TOP.v(280) has no driver
Warning (10034): Output port "ENET_RST_N" at DE2_TOP.v(281) has no driver
Warning (10034): Output port "ENET_CLK" at DE2_TOP.v(283) has no driver
Warning (10034): Output port "AUD_DACDAT" at DE2_TOP.v(288) has no driver
Warning (10034): Output port "AUD_XCK" at DE2_TOP.v(290) has no driver
Warning (10034): Output port "TD_RESET" at DE2_TOP.v(295) has no driver
Info: Elaborating entity "dds" for hierarchy "dds:u1"
Info: Elaborating entity "sum99" for hierarchy "dds:u1|sum99:b2v_inst"
Warning (10492): VHDL Process Statement warning at sum99.vhd(25): signal "temp" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file QQ.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: QQ
Info: Elaborating entity "QQ" for hierarchy "dds:u1|QQ:b2v_inst1"
Warning (10230): Verilog HDL assignment warning at QQ.v(6): truncated value with size 42 to match size of target (32)
Warning: Using design file reg3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: reg3-behav
    Info: Found entity 1: reg3
Info: Elaborating entity "reg3" for hierarchy "dds:u1|reg3:b2v_inst10"
Warning: Using design file reg1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: reg1-art
    Info: Found entity 1: reg1
Info: Elaborating entity "reg1" for hierarchy "dds:u1|reg1:b2v_inst2"
Warning: Using design file SEG7_LUT_8.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT_8
Info: Elaborating entity "SEG7_LUT_8" for hierarchy "dds:u1|SEG7_LUT_8:b2v_inst3"
Warning: Using design file SEG7_LUT.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: SEG7_LUT
Info: Elaborating entity "SEG7_LUT" for hierarchy "dds:u1|SEG7_LUT_8:b2v_inst3|SEG7_LUT:u0"
Warning: Using design file reg2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: reg2-art
    Info: Found entity 1: reg2
Info: Elaborating entity "reg2" for hierarchy "dds:u1|reg2:b2v_inst4"
Info: Elaborating entity "adder" for hierarchy "dds:u1|adder:b2v_inst5"
Info: Elaborating entity "sinrom" for hierarchy "dds:u1|sinrom:b2v_inst8"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_71a1.tdf
    Info: Found entity 1: altsyncram_71a1
Info: Elaborating entity "altsyncram_71a1" for hierarchy "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rsf2.tdf
    Info: Found entity 1: altsyncram_rsf2
Info: Elaborating entity "altsyncram_rsf2" for hierarchy "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|altsyncram_rsf2:altsyncram1"
Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd
    Info: Found design unit 1: sld_mod_ram_rom_pack
    Info: Found design unit 2: sld_mod_ram_rom-rtl
    Info: Found entity 1: sld_mod_ram_rom
Info: Elaborating entity "sld_mod_ram_rom" for hierarchy "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Elaborated megafunction instantiation "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Elaborating entity "sld_rom_sr" for hierarchy "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr"
Info: Elaborated megafunction instantiation "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr", which is child of megafunction instantiation "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2"
Info: Instantiated megafunction "dds:u1|sinrom:b2v_inst8|altsyncram:altsyncram_component|altsyncram_71a1:auto_generated|sld_mod_ram_rom:mgl_prim2" with the following parameter:
    Info: Parameter "CVALUE" = "0000000000"
    Info: Parameter "IS_DATA_IN_RAM" = "1"
    Info: Parameter "IS_READABLE" = "1"
    Info: Parameter "NODE_NAME" = "1919905073"
    Info: Parameter "NUMWORDS" = "1024"
    Info: Parameter "SHIFT_COUNT_BITS" = "4"
    Info: Parameter "WIDTH_WORD" = "10"
    Info: Parameter "WIDTHAD" = "10"
Warning: Port "en" on the entity instantiation of "u1" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be driven by GND.
Warning: Port "k" on the entity instantiation of "u1" is connected to a signal of width 1. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "p" on the entity instantiation of "u1" is connected to a signal of width 8. The formal width of the signal in the module is 10.  Extra bits will be driven by GND.
Warning: Port "reset" on the entity instantiation of "u1" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be driven by GND.
Error: Incremental instances created by tools that communicate with a device via the JTAG interface, such as SignalTap II Logic Analyzer, can only be supported when incremental compilation is set to Full incremental compilation
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 147 warnings
    Error: Processing ended: Tue Jul 24 15:43:45 2007
    Error: Elapsed time: 00:00:05


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; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/dds/dds/DE2_Top/DE2_TOP.map.smsg.