reg1.vhd

来自「一个经过DE2板验证的数字移相信号发生器的HDL原代码!曾经能够获奖的,工程设计」· VHDL 代码 · 共 16 行

library ieee;
use ieee.std_logic_1164.all;
entity reg1 is
   port (d: in std_logic_vector(9 downto 0);
         clk : in std_logic;
          q : out std_logic_vector(9 downto 0) );
end entity reg1;
architecture art of reg1 is
  begin 
  process(clk) is
    begin
    if clk'event and clk='1' then
       q<=d;
    end if;
  end process;
end architecture art;