sdram.c

基于AT91SAM7SE512cpu使用SDRAM的例子

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : SDRAM.c
//* Object              : init MT48LC16M16A2 Features Definition File
//* 1.0 18/May/06 JPP	: Creation
//*----------------------------------------------------------------------------

// Include Standard files
#include "project.h"
#include "SDRAM.h"
#include "AT91SAM7SE-EK.h"

//*----------------------------------------------------------------------------
//* \fn    AT91F_EBI_SDRAM_CfgPIO
//* \brief Configure the PIO for SDRAM check pinout connection
//*----------------------------------------------------------------------------
void AT91F_EBI_SDRAM_CfgPIO(void)
{
	// Configure PIO controllers to periph mode
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOA, // PIO controller base address
		0, // Peripheral A
		((unsigned int) AT91C_PA23_NWR1_NBS1_CFIOR_NUB) |
		((unsigned int) AT91C_PA24_SDA10   )            |
		((unsigned int) AT91C_PA25_SDCKE   )            |
		((unsigned int) AT91C_PA26_NCS1_SDCS)           |
		((unsigned int) AT91C_PA27_SDWE    )            |
		((unsigned int) AT91C_PA28_CAS     )            |
		((unsigned int) AT91C_PA29_RAS     )
		); // Peripheral B

	// Configure PIO controllers to periph mode
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOB, // PIO controller base address
		0, // Peripheral A
		((unsigned int) AT91C_PB1_A1_NBS2  ) |
		((unsigned int) AT91C_PB16_A16_BA0 ) |
		((unsigned int) AT91C_PB0_A0_NBS0  ) |
		((unsigned int) AT91C_PB2_A2       ) |
		((unsigned int) AT91C_PB3_A3       ) |
		((unsigned int) AT91C_PB4_A4       ) |
		((unsigned int) AT91C_PB10_A10     ) |
		((unsigned int) AT91C_PB5_A5       ) |
		((unsigned int) AT91C_PB11_A11     ) |
		((unsigned int) AT91C_PB6_A6       ) |
		((unsigned int) AT91C_PB12_A12     ) |
		((unsigned int) AT91C_PB7_A7       ) |
		((unsigned int) AT91C_PB13_A13     ) |
		((unsigned int) AT91C_PB8_A8       ) |
		((unsigned int) AT91C_PB14_A14     ) |
		((unsigned int) AT91C_PB9_A9       ) |
		((unsigned int) AT91C_PB15_A15     ) |
		((unsigned int) AT91C_PB17_A17_BA1 )); // Peripheral B
	// Configure PIO controllers to periph mode
	AT91F_PIO_CfgPeriph(
		AT91C_BASE_PIOC, // PIO controller base address

		((unsigned int) AT91C_PC10_D10 ) |
		((unsigned int) AT91C_PC11_D11 ) |
		((unsigned int) AT91C_PC12_D12 ) |
		((unsigned int) AT91C_PC13_D13 ) |
		((unsigned int) AT91C_PC14_D14 ) |
		((unsigned int) AT91C_PC15_D15 ) |
		((unsigned int) AT91C_PC0_D0   ) |
		((unsigned int) AT91C_PC1_D1   ) |
		((unsigned int) AT91C_PC2_D2   ) |
		((unsigned int) AT91C_PC3_D3   ) |
		((unsigned int) AT91C_PC4_D4   ) |
		((unsigned int) AT91C_PC5_D5   ) |
		((unsigned int) AT91C_PC6_D6   ) |
		((unsigned int) AT91C_PC7_D7   ) |
		((unsigned int) AT91C_PC8_D8   ) |
		((unsigned int) AT91C_PC9_D9   ) , // Peripheral A
		0); // Peripheral B

}
//*----------------------------------------------------------------------------
//* \fn    AT91F_InitSdram
//* \brief Init EBI and SDRAM controler for MT48LC16M16A2
//*----------------------------------------------------------------------------
void AT91F_InitSdram (void)
{
	volatile unsigned int i;
    AT91PS_SDRC	psdrc = AT91C_BASE_SDRC;

    // Init the EBI for SDRAM
    AT91C_BASE_EBI -> EBI_CSA =  AT91C_EBI_CS1A_SDRAMC;



	AT91F_EBI_SDRAM_CfgPIO();
    // Set Control Register
    psdrc->SDRC_CR =  AT91C_SDRC_NC_9         |  // 9  bits Column Addressing: 512 (A0-A8) AT91C_SDRC_NC_9
                      AT91C_SDRC_NR_13        |  // 13 bits Row Addressing     8K (A0-12)  AT91C_SDRC_NR_13
                      AT91C_SDRC_CAS_2        |  //  Check Table 8 for 7E(133) and 75(100) need CAS 2
                      AT91C_SDRC_NB_4_BANKS   |  // 4 banks
                      AT91C_SDRC_TWR_2        |
                      AT91C_SDRC_TRC_4        |
                      AT91C_SDRC_TRP_4        |
                      AT91C_SDRC_TRCD_2       |
                      AT91C_SDRC_TRAS_3       |
                      AT91C_SDRC_TXSR_4       ;
    // Wait time
	for (i =0; i< 1000;i++);

    // SDRAM initiazlization step
	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NOP_CMD;	// Set NOP
	*AT91C_SDRAM_BASE = 0x00000000;		                                // Perform NOP

	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS | 0x00000002;		        // Set PRCHG AL
	*AT91C_SDRAM_BASE	= 0x00000000;	                                // Perform PRCHG

    // Wait time
	for (i =0; i< 10000;i++);

	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 1st CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR = AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 2 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 3 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 4 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS |AT91C_SDRC_MODE_RFSH_CMD;	// Set 5 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 6 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 7 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;// Set 8 CBR
    *AT91C_SDRAM_BASE = 0x00000000;	                                    // Perform CBR

	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_LMR_CMD;	// Set LMR operation
	*(AT91C_SDRAM_BASE  + 20)= 0xcafedede;	                            // Perform LMR burst=1, lat=2

    // Set Refresh Timer
	psdrc->SDRC_TR	= AT91C_SDRC_TR_TIME;
	psdrc->SDRC_MR	= AT91C_SDRC_DBW_16_BITS ;    // Set Normal mode // 16 bits
	*AT91C_SDRAM_BASE= 0x00000000;	              // Perform Normal mode
}