xilleonreg_kernel.h

for mips adm5120 uclibc-0.9.19 toolchain

#define mmMIPS_EXT_PCI_INT_CNTL                                      0x0A30

#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR0_EN__SIZE                   1
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR0_EN__MASK                   0x00000001
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR0_EN__SHIFT                  0
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR1_EN__SIZE                   1
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR1_EN__MASK                   0x00000002
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR1_EN__SHIFT                  1
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR2_EN__SIZE                   1
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR2_EN__MASK                   0x00000004
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR2_EN__SHIFT                  2
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR3_EN__SIZE                   1
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR3_EN__MASK                   0x00000008
#define MIPS_EXT_PCI_INT_CNTL__MIPS_INTR3_EN__SHIFT                  3

/* REGISTER:  EXT_PCI_INT_STATUS */

#define EXT_PCI_INT_STATUS__SIZE                                     32
#define EXT_PCI_INT_STATUS__BYTELANE                                 0
#define EXT_PCI_INT_STATUS__WRMASK                                   0x00000000
#define EXT_PCI_INT_STATUS__RDMASK                                   0x0000000f
#define EXT_PCI_INT_STATUS__WOMASK                                   0x00000000

#define mmEXT_PCI_INT_STATUS                                         0x0A0C

#define EXT_PCI_INT_STATUS__INTR0__SIZE                              1
#define EXT_PCI_INT_STATUS__INTR0__MASK                              0x00000001
#define EXT_PCI_INT_STATUS__INTR0__SHIFT                             0
#define EXT_PCI_INT_STATUS__INTR1__SIZE                              1
#define EXT_PCI_INT_STATUS__INTR1__MASK                              0x00000002
#define EXT_PCI_INT_STATUS__INTR1__SHIFT                             1
#define EXT_PCI_INT_STATUS__INTR2__SIZE                              1
#define EXT_PCI_INT_STATUS__INTR2__MASK                              0x00000004
#define EXT_PCI_INT_STATUS__INTR2__SHIFT                             2
#define EXT_PCI_INT_STATUS__INTR3__SIZE                              1
#define EXT_PCI_INT_STATUS__INTR3__MASK                              0x00000008
#define EXT_PCI_INT_STATUS__INTR3__SHIFT                             3

/* REGISTER:  MIPS_PCU_INT_CNTL */

#define MIPS_PCU_INT_CNTL__SIZE                                      32
#define MIPS_PCU_INT_CNTL__BYTELANE                                  0
#define MIPS_PCU_INT_CNTL__WRMASK                                    0x007fff3f
#define MIPS_PCU_INT_CNTL__RDMASK                                    0x007fff3f
#define MIPS_PCU_INT_CNTL__WOMASK                                    0x00000000

#define mmMIPS_PCU_INT_CNTL                                          0x0A34

#define MIPS_PCU_INT_CNTL__MIPS_DMA_INT_EN__SIZE                     1
#define MIPS_PCU_INT_CNTL__MIPS_DMA_INT_EN__MASK                     0x00000001
#define MIPS_PCU_INT_CNTL__MIPS_DMA_INT_EN__SHIFT                    0
#define MIPS_PCU_INT_CNTL__MIPS_UIRT_EN__SIZE                        1
#define MIPS_PCU_INT_CNTL__MIPS_UIRT_EN__MASK                        0x00000002
#define MIPS_PCU_INT_CNTL__MIPS_UIRT_EN__SHIFT                       1
#define MIPS_PCU_INT_CNTL__MIPS_UART1_EN__SIZE                       1
#define MIPS_PCU_INT_CNTL__MIPS_UART1_EN__MASK                       0x00000004
#define MIPS_PCU_INT_CNTL__MIPS_UART1_EN__SHIFT                      2
#define MIPS_PCU_INT_CNTL__MIPS_UART2_EN__SIZE                       1
#define MIPS_PCU_INT_CNTL__MIPS_UART2_EN__MASK                       0x00000008
#define MIPS_PCU_INT_CNTL__MIPS_UART2_EN__SHIFT                      3
#define MIPS_PCU_INT_CNTL__MIPS_TIMER_GLOBAL_INT_EN__SIZE            1
#define MIPS_PCU_INT_CNTL__MIPS_TIMER_GLOBAL_INT_EN__MASK            0x00000010
#define MIPS_PCU_INT_CNTL__MIPS_TIMER_GLOBAL_INT_EN__SHIFT           4
#define MIPS_PCU_INT_CNTL__MIPS_RTC_GLOBAL_INT_EN__SIZE              1
#define MIPS_PCU_INT_CNTL__MIPS_RTC_GLOBAL_INT_EN__MASK              0x00000020
#define MIPS_PCU_INT_CNTL__MIPS_RTC_GLOBAL_INT_EN__SHIFT             5
#define MIPS_PCU_INT_CNTL__MIPS_FLEXBUS_INT_EN__SIZE                 8
#define MIPS_PCU_INT_CNTL__MIPS_FLEXBUS_INT_EN__MASK                 0x0000ff00
#define MIPS_PCU_INT_CNTL__MIPS_FLEXBUS_INT_EN__SHIFT                8
#define MIPS_PCU_INT_CNTL__MIPS_I2C0_INT_EN__SIZE                    1
#define MIPS_PCU_INT_CNTL__MIPS_I2C0_INT_EN__MASK                    0x00010000
#define MIPS_PCU_INT_CNTL__MIPS_I2C0_INT_EN__SHIFT                   16
#define MIPS_PCU_INT_CNTL__MIPS_I2C1_INT_EN__SIZE                    1
#define MIPS_PCU_INT_CNTL__MIPS_I2C1_INT_EN__MASK                    0x00020000
#define MIPS_PCU_INT_CNTL__MIPS_I2C1_INT_EN__SHIFT                   17
#define MIPS_PCU_INT_CNTL__MIPS_SMCA_INT_EN__SIZE                    1
#define MIPS_PCU_INT_CNTL__MIPS_SMCA_INT_EN__MASK                    0x00040000
#define MIPS_PCU_INT_CNTL__MIPS_SMCA_INT_EN__SHIFT                   18
#define MIPS_PCU_INT_CNTL__MIPS_SMCB_INT_EN__SIZE                    1
#define MIPS_PCU_INT_CNTL__MIPS_SMCB_INT_EN__MASK                    0x00080000
#define MIPS_PCU_INT_CNTL__MIPS_SMCB_INT_EN__SHIFT                   19
#define MIPS_PCU_INT_CNTL__MIPS_SMCC_INT_EN__SIZE                    1
#define MIPS_PCU_INT_CNTL__MIPS_SMCC_INT_EN__MASK                    0x00100000
#define MIPS_PCU_INT_CNTL__MIPS_SMCC_INT_EN__SHIFT                   20
#define MIPS_PCU_INT_CNTL__MIPS_HDCP_AUTHORIZED_INT_EN__SIZE         1
#define MIPS_PCU_INT_CNTL__MIPS_HDCP_AUTHORIZED_INT_EN__MASK         0x00200000
#define MIPS_PCU_INT_CNTL__MIPS_HDCP_AUTHORIZED_INT_EN__SHIFT        21
#define MIPS_PCU_INT_CNTL__MIPS_DVI_I2C_INT_EN__SIZE                 1
#define MIPS_PCU_INT_CNTL__MIPS_DVI_I2C_INT_EN__MASK                 0x00400000
#define MIPS_PCU_INT_CNTL__MIPS_DVI_I2C_INT_EN__SHIFT                22


/* REGISTER:  PCU_INT_STATUS */

#define PCU_INT_STATUS__SIZE                                         32
#define PCU_INT_STATUS__BYTELANE                                     0
#define PCU_INT_STATUS__WRMASK                                       0x00630000
#define PCU_INT_STATUS__RDMASK                                       0x007fff3f
#define PCU_INT_STATUS__WOMASK                                       0x00000000

#define mmPCU_INT_STATUS                                             0x0A14

#define PCU_INT_STATUS__DMA_INT__SIZE                                1
#define PCU_INT_STATUS__DMA_INT__MASK                                0x00000001
#define PCU_INT_STATUS__DMA_INT__SHIFT                               0
#define PCU_INT_STATUS__UIRT_INT__SIZE                               1
#define PCU_INT_STATUS__UIRT_INT__MASK                               0x00000002
#define PCU_INT_STATUS__UIRT_INT__SHIFT                              1
#define PCU_INT_STATUS__UART1_INT__SIZE                              1
#define PCU_INT_STATUS__UART1_INT__MASK                              0x00000004
#define PCU_INT_STATUS__UART1_INT__SHIFT                             2
#define PCU_INT_STATUS__UART2_INT__SIZE                              1
#define PCU_INT_STATUS__UART2_INT__MASK                              0x00000008
#define PCU_INT_STATUS__UART2_INT__SHIFT                             3
#define PCU_INT_STATUS__TIMER_GLOBAL__SIZE                           1
#define PCU_INT_STATUS__TIMER_GLOBAL__MASK                           0x00000010
#define PCU_INT_STATUS__TIMER_GLOBAL__SHIFT                          4
#define PCU_INT_STATUS__RTC_GLOBAL_INT__SIZE                         1
#define PCU_INT_STATUS__RTC_GLOBAL_INT__MASK                         0x00000020
#define PCU_INT_STATUS__RTC_GLOBAL_INT__SHIFT                        5
#define PCU_INT_STATUS__FLEXBUS_INT_0__SIZE                          1
#define PCU_INT_STATUS__FLEXBUS_INT_0__MASK                          0x00000100
#define PCU_INT_STATUS__FLEXBUS_INT_0__SHIFT                         8
#define PCU_INT_STATUS__FLEXBUS_INT_1__SIZE                          1
#define PCU_INT_STATUS__FLEXBUS_INT_1__MASK                          0x00000200
#define PCU_INT_STATUS__FLEXBUS_INT_1__SHIFT                         9
#define PCU_INT_STATUS__FLEXBUS_INT_2__SIZE                          1
#define PCU_INT_STATUS__FLEXBUS_INT_2__MASK                          0x00000400
#define PCU_INT_STATUS__FLEXBUS_INT_2__SHIFT                         10
#define PCU_INT_STATUS__FLEXBUS_INT_3__SIZE                          1
#define PCU_INT_STATUS__FLEXBUS_INT_3__MASK                          0x00000800
#define PCU_INT_STATUS__FLEXBUS_INT_3__SHIFT                         11
#define PCU_INT_STATUS__FLEXBUS_INT_4__SIZE                          1
#define PCU_INT_STATUS__FLEXBUS_INT_4__MASK                          0x00001000
#define PCU_INT_STATUS__FLEXBUS_INT_4__SHIFT                         12
#define PCU_INT_STATUS__FLEXBUS_INT_5__SIZE                          1
#define PCU_INT_STATUS__FLEXBUS_INT_5__MASK                          0x00002000
#define PCU_INT_STATUS__FLEXBUS_INT_5__SHIFT                         13
#define PCU_INT_STATUS__FLEXBUS_INT_6__SIZE                          1
#define PCU_INT_STATUS__FLEXBUS_INT_6__MASK                          0x00004000
#define PCU_INT_STATUS__FLEXBUS_INT_6__SHIFT                         14
#define PCU_INT_STATUS__FLEXBUS_INT_7__SIZE                          1
#define PCU_INT_STATUS__FLEXBUS_INT_7__MASK                          0x00008000
#define PCU_INT_STATUS__FLEXBUS_INT_7__SHIFT                         15
#define PCU_INT_STATUS__I2C0_INT__SIZE                               1
#define PCU_INT_STATUS__I2C0_INT__MASK                               0x00010000
#define PCU_INT_STATUS__I2C0_INT__SHIFT                              16
#define PCU_INT_STATUS__I2C0_INT_AK__SIZE                            1
#define PCU_INT_STATUS__I2C0_INT_AK__MASK                            0x00010000
#define PCU_INT_STATUS__I2C0_INT_AK__SHIFT                           16
#define PCU_INT_STATUS__I2C1_INT__SIZE                               1
#define PCU_INT_STATUS__I2C1_INT__MASK                               0x00020000
#define PCU_INT_STATUS__I2C1_INT__SHIFT                              17
#define PCU_INT_STATUS__I2C1_INT_AK__SIZE                            1
#define PCU_INT_STATUS__I2C1_INT_AK__MASK                            0x00020000
#define PCU_INT_STATUS__I2C1_INT_AK__SHIFT                           17
#define PCU_INT_STATUS__SMCA_INT__SIZE                               1
#define PCU_INT_STATUS__SMCA_INT__MASK                               0x00040000
#define PCU_INT_STATUS__SMCA_INT__SHIFT                              18
#define PCU_INT_STATUS__SMCB_INT__SIZE                               1
#define PCU_INT_STATUS__SMCB_INT__MASK                               0x00080000
#define PCU_INT_STATUS__SMCB_INT__SHIFT                              19
#define PCU_INT_STATUS__SMCC_INT__SIZE                               1
#define PCU_INT_STATUS__SMCC_INT__MASK                               0x00100000
#define PCU_INT_STATUS__SMCC_INT__SHIFT                              20
#define PCU_INT_STATUS__HDCP_AUTHORIZED_INT_STAT__SIZE               1
#define PCU_INT_STATUS__HDCP_AUTHORIZED_INT_STAT__MASK               0x00200000
#define PCU_INT_STATUS__HDCP_AUTHORIZED_INT_STAT__SHIFT              21
#define PCU_INT_STATUS__HDCP_AUTHORIZED_INT_AK__SIZE                 1
#define PCU_INT_STATUS__HDCP_AUTHORIZED_INT_AK__MASK                 0x00200000
#define PCU_INT_STATUS__HDCP_AUTHORIZED_INT_AK__SHIFT                21
#define PCU_INT_STATUS__DVI_I2C_INT_STAT__SIZE                       1
#define PCU_INT_STATUS__DVI_I2C_INT_STAT__MASK                       0x00400000
#define PCU_INT_STATUS__DVI_I2C_INT_STAT__SHIFT                      22
#define PCU_INT_STATUS__DVI_I2C_INT_AK__SIZE                         1
#define PCU_INT_STATUS__DVI_I2C_INT_AK__MASK                         0x00400000
#define PCU_INT_STATUS__DVI_I2C_INT_AK__SHIFT                        22


/* REGISTER:  MIPS_SB_INT_CNTL */

#define MIPS_SB_INT_CNTL__SIZE                                       32
#define MIPS_SB_INT_CNTL__BYTELANE                                   0
#define MIPS_SB_INT_CNTL__WRMASK                                     0x000003f3
#define MIPS_SB_INT_CNTL__RDMASK                                     0x000003f3
#define MIPS_SB_INT_CNTL__WOMASK                                     0x00000000

#define mmMIPS_SB_INT_CNTL                                           0x0A38

#define MIPS_SB_INT_CNTL__MIPS_IDE_INT_EN__SIZE                      1
#define MIPS_SB_INT_CNTL__MIPS_IDE_INT_EN__MASK                      0x00000001
#define MIPS_SB_INT_CNTL__MIPS_IDE_INT_EN__SHIFT                     0
#define MIPS_SB_INT_CNTL__MIPS_USB_INT_EN_0__SIZE                    1
#define MIPS_SB_INT_CNTL__MIPS_USB_INT_EN_0__MASK                    0x00000002
#define MIPS_SB_INT_CNTL__MIPS_USB_INT_EN_0__SHIFT                   1
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_0__SIZE                    1
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_0__MASK                    0x00000010
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_0__SHIFT                   4
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_1__SIZE                    1
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_1__MASK                    0x00000020
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_1__SHIFT                   5
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_2__SIZE                    1
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_2__MASK                    0x00000040
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_2__SHIFT                   6
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_3__SIZE                    1
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_3__MASK                    0x00000080
#define MIPS_SB_INT_CNTL__MIPS_LPC_INT_EN_3__SHIFT                   7
#define MIPS_SB_INT_CNTL__MIPS_DAIO_INT_EN_0__SIZE                   1
#define MIPS_SB_INT_CNTL__MIPS_DAIO_INT_EN_0__MASK                   0x00000100
#define MIPS_SB_INT_CNTL__MIPS_DAIO_INT_