📄 xilleonreg_kernel.h
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#define MIPS_GEN_INT_CNTL__MIPS_BUSMASTER_EOL_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_BUSMASTER_EOL_INT_EN__MASK 0x00010000#define MIPS_GEN_INT_CNTL__MIPS_BUSMASTER_EOL_INT_EN__SHIFT 16#define MIPS_GEN_INT_CNTL__MIPS_CRTC_VBLANK_BIT2_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_CRTC_VBLANK_BIT2_INT_EN__MASK 0x00020000#define MIPS_GEN_INT_CNTL__MIPS_CRTC_VBLANK_BIT2_INT_EN__SHIFT 17#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VBLANK_BIT2_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VBLANK_BIT2_INT_EN__MASK 0x00040000#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VBLANK_BIT2_INT_EN__SHIFT 18#define MIPS_GEN_INT_CNTL__MIPS_SI_MIPS_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_SI_MIPS_INT_EN__MASK 0x00100000#define MIPS_GEN_INT_CNTL__MIPS_SI_MIPS_INT_EN__SHIFT 20#define MIPS_GEN_INT_CNTL__MIPS_SI_CPU_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_SI_CPU_INT_EN__MASK 0x00200000#define MIPS_GEN_INT_CNTL__MIPS_SI_CPU_INT_EN__SHIFT 21#define MIPS_GEN_INT_CNTL__MIPS_AUDIO_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_AUDIO_INT_EN__MASK 0x00400000#define MIPS_GEN_INT_CNTL__MIPS_AUDIO_INT_EN__SHIFT 22#define MIPS_GEN_INT_CNTL__MIPS_PCIC_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_PCIC_INT_EN__MASK 0x00800000#define MIPS_GEN_INT_CNTL__MIPS_PCIC_INT_EN__SHIFT 23#define MIPS_GEN_INT_CNTL__MIPS_VIPH_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_VIPH_INT_EN__MASK 0x01000000#define MIPS_GEN_INT_CNTL__MIPS_VIPH_INT_EN__SHIFT 24#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VBLANK_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VBLANK_INT_EN__MASK 0x02000000#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VBLANK_INT_EN__SHIFT 25#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VLINE_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VLINE_INT_EN__MASK 0x04000000#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VLINE_INT_EN__SHIFT 26#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VSYNC_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VSYNC_INT_EN__MASK 0x08000000#define MIPS_GEN_INT_CNTL__MIPS_CRTC1_VSYNC_INT_EN__SHIFT 27#define MIPS_GEN_INT_CNTL__MIPS_SOUTHBRIDGE_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_SOUTHBRIDGE_INT_EN__MASK 0x10000000#define MIPS_GEN_INT_CNTL__MIPS_SOUTHBRIDGE_INT_EN__SHIFT 28#define MIPS_GEN_INT_CNTL__MIPS_SNAPSHOT1_INT_EN__SIZE 1#define MIPS_GEN_INT_CNTL__MIPS_SNAPSHOT1_INT_EN__MASK 0x20000000#define MIPS_GEN_INT_CNTL__MIPS_SNAPSHOT1_INT_EN__SHIFT 29/* REGISTER: GEN_INT_STATUS */#define GEN_INT_STATUS__SIZE 32#define GEN_INT_STATUS__BYTELANE 0#define GEN_INT_STATUS__WRMASK 0x2e07580f#define GEN_INT_STATUS__RDMASK 0xbff7dfff#define GEN_INT_STATUS__WOMASK 0x00000000#define mmGEN_INT_STATUS 0x0044#define blockioGEN_INT_STATUS 0x0044#define GEN_INT_STATUS__CRTC_VBLANK_INT__SIZE 1#define GEN_INT_STATUS__CRTC_VBLANK_INT__MASK 0x00000001#define GEN_INT_STATUS__CRTC_VBLANK_INT__SHIFT 0#define GEN_INT_STATUS__CRTC_VBLANK_INT_AK__SIZE 1#define GEN_INT_STATUS__CRTC_VBLANK_INT_AK__MASK 0x00000001#define GEN_INT_STATUS__CRTC_VBLANK_INT_AK__SHIFT 0#define GEN_INT_STATUS__CRTC_VLINE_INT__SIZE 1#define GEN_INT_STATUS__CRTC_VLINE_INT__MASK 0x00000002#define GEN_INT_STATUS__CRTC_VLINE_INT__SHIFT 1#define GEN_INT_STATUS__CRTC_VLINE_INT_AK__SIZE 1#define GEN_INT_STATUS__CRTC_VLINE_INT_AK__MASK 0x00000002#define GEN_INT_STATUS__CRTC_VLINE_INT_AK__SHIFT 1#define GEN_INT_STATUS__CRTC_VSYNC_INT__SIZE 1#define GEN_INT_STATUS__CRTC_VSYNC_INT__MASK 0x00000004#define GEN_INT_STATUS__CRTC_VSYNC_INT__SHIFT 2#define GEN_INT_STATUS__CRTC_VSYNC_INT_AK__SIZE 1#define GEN_INT_STATUS__CRTC_VSYNC_INT_AK__MASK 0x00000004#define GEN_INT_STATUS__CRTC_VSYNC_INT_AK__SHIFT 2#define GEN_INT_STATUS__SNAPSHOT_INT__SIZE 1#define GEN_INT_STATUS__SNAPSHOT_INT__MASK 0x00000008#define GEN_INT_STATUS__SNAPSHOT_INT__SHIFT 3#define GEN_INT_STATUS__SNAPSHOT_INT_AK__SIZE 1#define GEN_INT_STATUS__SNAPSHOT_INT_AK__MASK 0x00000008#define GEN_INT_STATUS__SNAPSHOT_INT_AK__SHIFT 3#define GEN_INT_STATUS__HM_COM_MIPS_INT__SIZE 1#define GEN_INT_STATUS__HM_COM_MIPS_INT__MASK 0x00000010#define GEN_INT_STATUS__HM_COM_MIPS_INT__SHIFT 4#define GEN_INT_STATUS__HM_COM_CPU_INT__SIZE 1#define GEN_INT_STATUS__HM_COM_CPU_INT__MASK 0x00000020#define GEN_INT_STATUS__HM_COM_CPU_INT__SHIFT 5#define GEN_INT_STATUS__TPS_MIPS_INT__SIZE 1#define GEN_INT_STATUS__TPS_MIPS_INT__MASK 0x00000040#define GEN_INT_STATUS__TPS_MIPS_INT__SHIFT 6#define GEN_INT_STATUS__TPS_CPU_INT__SIZE 1#define GEN_INT_STATUS__TPS_CPU_INT__MASK 0x00000080#define GEN_INT_STATUS__TPS_CPU_INT__SHIFT 7#define GEN_INT_STATUS__VIDCAP_INT__SIZE 1#define GEN_INT_STATUS__VIDCAP_INT__MASK 0x00000100#define GEN_INT_STATUS__VIDCAP_INT__SHIFT 8#define GEN_INT_STATUS__MPEG1_INT_ACTIVE__SIZE 1#define GEN_INT_STATUS__MPEG1_INT_ACTIVE__MASK 0x00000200#define GEN_INT_STATUS__MPEG1_INT_ACTIVE__SHIFT 9#define GEN_INT_STATUS__MPEG_INT_ACTIVE__SIZE 1#define GEN_INT_STATUS__MPEG_INT_ACTIVE__MASK 0x00000400#define GEN_INT_STATUS__MPEG_INT_ACTIVE__SHIFT 10#define GEN_INT_STATUS__FP2_DETECT_STAT__SIZE 1#define GEN_INT_STATUS__FP2_DETECT_STAT__MASK 0x00000800#define GEN_INT_STATUS__FP2_DETECT_STAT__SHIFT 11#define GEN_INT_STATUS__FP2_DETECT_STAT_AK__SIZE 1#define GEN_INT_STATUS__FP2_DETECT_STAT_AK__MASK 0x00000800#define GEN_INT_STATUS__FP2_DETECT_STAT_AK__SHIFT 11#define GEN_INT_STATUS__VLB_OP_INT__SIZE 1#define GEN_INT_STATUS__VLB_OP_INT__MASK 0x00001000#define GEN_INT_STATUS__VLB_OP_INT__SHIFT 12#define GEN_INT_STATUS__VLB_OP_INT_AK__SIZE 1#define GEN_INT_STATUS__VLB_OP_INT_AK__MASK 0x00001000#define GEN_INT_STATUS__VLB_OP_INT_AK__SHIFT 12#define GEN_INT_STATUS__EXT_I2C_DATA_REQ_INT__SIZE 1#define GEN_INT_STATUS__EXT_I2C_DATA_REQ_INT__MASK 0x00004000#define GEN_INT_STATUS__EXT_I2C_DATA_REQ_INT__SHIFT 14#define GEN_INT_STATUS__EXT_I2C_DATA_REQ_INT_AK__SIZE 1#define GEN_INT_STATUS__EXT_I2C_DATA_REQ_INT_AK__MASK 0x00004000#define GEN_INT_STATUS__EXT_I2C_DATA_REQ_INT_AK__SHIFT 14#define GEN_INT_STATUS__PCU_INT__SIZE 1#define GEN_INT_STATUS__PCU_INT__MASK 0x00008000#define GEN_INT_STATUS__PCU_INT__SHIFT 15#define GEN_INT_STATUS__BUSMASTER_EOL_INT__SIZE 1#define GEN_INT_STATUS__BUSMASTER_EOL_INT__MASK 0x00010000#define GEN_INT_STATUS__BUSMASTER_EOL_INT__SHIFT 16#define GEN_INT_STATUS__BUSMASTER_EOL_INT_AK__SIZE 1#define GEN_INT_STATUS__BUSMASTER_EOL_INT_AK__MASK 0x00010000#define GEN_INT_STATUS__BUSMASTER_EOL_INT_AK__SHIFT 16#define GEN_INT_STATUS__CRTC_VBLANK_BIT2_INT__SIZE 1#define GEN_INT_STATUS__CRTC_VBLANK_BIT2_INT__MASK 0x00020000#define GEN_INT_STATUS__CRTC_VBLANK_BIT2_INT__SHIFT 17#define GEN_INT_STATUS__CRTC_VBLANK_BIT2_INT_AK__SIZE 1#define GEN_INT_STATUS__CRTC_VBLANK_BIT2_INT_AK__MASK 0x00020000#define GEN_INT_STATUS__CRTC_VBLANK_BIT2_INT_AK__SHIFT 17#define GEN_INT_STATUS__CRTC1_VBLANK_BIT2_INT__SIZE 1#define GEN_INT_STATUS__CRTC1_VBLANK_BIT2_INT__MASK 0x00040000#define GEN_INT_STATUS__CRTC1_VBLANK_BIT2_INT__SHIFT 18#define GEN_INT_STATUS__CRTC1_VBLANK_BIT2_INT_AK__SIZE 1#define GEN_INT_STATUS__CRTC1_VBLANK_BIT2_INT_AK__MASK 0x00040000#define GEN_INT_STATUS__CRTC1_VBLANK_BIT2_INT_AK__SHIFT 18#define GEN_INT_STATUS__SI_MIPS_INT__SIZE 1#define GEN_INT_STATUS__SI_MIPS_INT__MASK 0x00100000#define GEN_INT_STATUS__SI_MIPS_INT__SHIFT 20#define GEN_INT_STATUS__SI_CPU_INT__SIZE 1#define GEN_INT_STATUS__SI_CPU_INT__MASK 0x00200000#define GEN_INT_STATUS__SI_CPU_INT__SHIFT 21#define GEN_INT_STATUS__AUDIO_INT__SIZE 1#define GEN_INT_STATUS__AUDIO_INT__MASK 0x00400000#define GEN_INT_STATUS__AUDIO_INT__SHIFT 22#define GEN_INT_STATUS__PCIC_INT__SIZE 1#define GEN_INT_STATUS__PCIC_INT__MASK 0x00800000#define GEN_INT_STATUS__PCIC_INT__SHIFT 23#define GEN_INT_STATUS__VIPH_INT__SIZE 1#define GEN_INT_STATUS__VIPH_INT__MASK 0x01000000#define GEN_INT_STATUS__VIPH_INT__SHIFT 24#define GEN_INT_STATUS__CRTC1_VBLANK_INT__SIZE 1#define GEN_INT_STATUS__CRTC1_VBLANK_INT__MASK 0x02000000#define GEN_INT_STATUS__CRTC1_VBLANK_INT__SHIFT 25#define GEN_INT_STATUS__CRTC1_VBLANK_INT_AK__SIZE 1#define GEN_INT_STATUS__CRTC1_VBLANK_INT_AK__MASK 0x02000000#define GEN_INT_STATUS__CRTC1_VBLANK_INT_AK__SHIFT 25#define GEN_INT_STATUS__CRTC1_VLINE_INT__SIZE 1#define GEN_INT_STATUS__CRTC1_VLINE_INT__MASK 0x04000000#define GEN_INT_STATUS__CRTC1_VLINE_INT__SHIFT 26#define GEN_INT_STATUS__CRTC1_VLINE_INT_AK__SIZE 1#define GEN_INT_STATUS__CRTC1_VLINE_INT_AK__MASK 0x04000000#define GEN_INT_STATUS__CRTC1_VLINE_INT_AK__SHIFT 26#define GEN_INT_STATUS__CRTC1_VSYNC_INT__SIZE 1#define GEN_INT_STATUS__CRTC1_VSYNC_INT__MASK 0x08000000#define GEN_INT_STATUS__CRTC1_VSYNC_INT__SHIFT 27#define GEN_INT_STATUS__CRTC1_VSYNC_INT_AK__SIZE 1#define GEN_INT_STATUS__CRTC1_VSYNC_INT_AK__MASK 0x08000000#define GEN_INT_STATUS__CRTC1_VSYNC_INT_AK__SHIFT 27#define GEN_INT_STATUS__SOUTHBRIDGE_INT__SIZE 1#define GEN_INT_STATUS__SOUTHBRIDGE_INT__MASK 0x10000000#define GEN_INT_STATUS__SOUTHBRIDGE_INT__SHIFT 28#define GEN_INT_STATUS__SNAPSHOT1_INT__SIZE 1#define GEN_INT_STATUS__SNAPSHOT1_INT__MASK 0x20000000#define GEN_INT_STATUS__SNAPSHOT1_INT__SHIFT 29#define GEN_INT_STATUS__SNAPSHOT1_INT_AK__SIZE 1#define GEN_INT_STATUS__SNAPSHOT1_INT_AK__MASK 0x20000000#define GEN_INT_STATUS__SNAPSHOT1_INT_AK__SHIFT 29#define GEN_INT_STATUS__CHIP_INT__SIZE 1#define GEN_INT_STATUS__CHIP_INT__MASK 0x80000000#define GEN_INT_STATUS__CHIP_INT__SHIFT 31/* REGISTER: PAD_PCI */#define PAD_PCI__SIZE 32#define PAD_PCI__BYTELANE 0#define PAD_PCI__WRMASK 0x000003ff#define PAD_PCI__RDMASK 0x000003ff#define PAD_PCI__WOMASK 0x00000000#define mmPAD_PCI 0x0958#define PAD_PCI__PCI_SRN__SIZE 1#define PAD_PCI__PCI_SRN__MASK 0x00000001#define PAD_PCI__PCI_SRN__SHIFT 0#define PAD_PCI__PCI_SRP__SIZE 1#define PAD_PCI__PCI_SRP__MASK 0x00000002#define PAD_PCI__PCI_SRP__SHIFT 1#define PAD_PCI__PCI_SP__SIZE 4#define PAD_PCI__PCI_SP__MASK 0x0000003c#define PAD_PCI__PCI_SP__SHIFT 2#define PAD_PCI__PCI_SN__SIZE 4#define PAD_PCI__PCI_SN__MASK 0x000003c0#define PAD_PCI__PCI_SN__SHIFT 6/* REGISTER: MIPS_EXT_PCI_INT_CNTL */#define MIPS_EXT_PCI_INT_CNTL__SIZE 32#define MIPS_EXT_PCI_INT_CNTL__BYTELANE 0#define MIPS_EXT_PCI_INT_CNTL__WRMASK 0x0000000f#define MIPS_EXT_PCI_INT_CNTL__RDMASK 0x0000000f#define MIPS_EXT_PCI_INT_CNTL__WOMASK 0x00000000⌨️ 快捷键说明
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