xilleonreg_kernel.h

for mips adm5120 uclibc-0.9.19 toolchain

#define GPIOB_DATA_FROM_PAD__SIZE                                    32
#define GPIOB_DATA_FROM_PAD__BYTELANE                                0
#define GPIOB_DATA_FROM_PAD__WRMASK                                  0x00000000
#define GPIOB_DATA_FROM_PAD__RDMASK                                  0x000fffff
#define GPIOB_DATA_FROM_PAD__WOMASK                                  0x00000000

#define mmGPIOB_DATA_FROM_PAD                                        0x08A4

#define GPIOB_DATA_FROM_PAD__GPIO_DATA_B__SIZE                       20
#define GPIOB_DATA_FROM_PAD__GPIO_DATA_B__MASK                       0x000fffff
#define GPIOB_DATA_FROM_PAD__GPIO_DATA_B__SHIFT                      0



/* REGISTER:  LED_BASE */

#define mmLED_BASE                                                   0x440000


/* REGISTER:  APER_PCU_IPA_ADDR */

#define APER_PCU_IPA_ADDR__SIZE                                      32
#define APER_PCU_IPA_ADDR__BYTELANE                                  0
#define APER_PCU_IPA_ADDR__WRMASK                                    0xffffffff
#define APER_PCU_IPA_ADDR__RDMASK                                    0xffffffff
#define APER_PCU_IPA_ADDR__WOMASK                                    0x00000000

#define mmAPER_PCU_IPA_ADDR                                          0x2800

#define APER_PCU_IPA_ADDR__BASE_ADDRESS__SIZE                        16
#define APER_PCU_IPA_ADDR__BASE_ADDRESS__MASK                        0x0000ffff
#define APER_PCU_IPA_ADDR__BASE_ADDRESS__SHIFT                       0
#define APER_PCU_IPA_ADDR__BASE_OUT__SIZE                            16
#define APER_PCU_IPA_ADDR__BASE_OUT__MASK                            0xffff0000
#define APER_PCU_IPA_ADDR__BASE_OUT__SHIFT                           16

/* REGISTER:  APER_PCU_IPA_CNTL */

#define APER_PCU_IPA_CNTL__SIZE                                      32
#define APER_PCU_IPA_CNTL__BYTELANE                                  0
#define APER_PCU_IPA_CNTL__WRMASK                                    0x0000000f
#define APER_PCU_IPA_CNTL__RDMASK                                    0x0000000f
#define APER_PCU_IPA_CNTL__WOMASK                                    0x00000000

#define mmAPER_PCU_IPA_CNTL                                          0x4404

#define APER_PCU_IPA_CNTL__APERSIZE__SIZE                            4
#define APER_PCU_IPA_CNTL__APERSIZE__MASK                            0x0000000f
#define APER_PCU_IPA_CNTL__APERSIZE__SHIFT                           0


/* REGISTER:  APER_PCU_SFLASH_ADDR */

#define APER_PCU_SFLASH_ADDR__SIZE                                   32
#define APER_PCU_SFLASH_ADDR__BYTELANE                               0
#define APER_PCU_SFLASH_ADDR__WRMASK                                 0xffffffff
#define APER_PCU_SFLASH_ADDR__RDMASK                                 0xffffffff
#define APER_PCU_SFLASH_ADDR__WOMASK                                 0x00000000

#define mmAPER_PCU_SFLASH_ADDR                                       0x2808

#define APER_PCU_SFLASH_ADDR__BASE_ADDRESS__SIZE                     16
#define APER_PCU_SFLASH_ADDR__BASE_ADDRESS__MASK                     0x0000ffff
#define APER_PCU_SFLASH_ADDR__BASE_ADDRESS__SHIFT                    0
#define APER_PCU_SFLASH_ADDR__BASE_OUT__SIZE                         16
#define APER_PCU_SFLASH_ADDR__BASE_OUT__MASK                         0xffff0000
#define APER_PCU_SFLASH_ADDR__BASE_OUT__SHIFT                        16

/* REGISTER:  APER_PCU_SFLASH_CNTL */

#define APER_PCU_SFLASH_CNTL__SIZE                                   32
#define APER_PCU_SFLASH_CNTL__BYTELANE                               0
#define APER_PCU_SFLASH_CNTL__WRMASK                                 0x0000000f
#define APER_PCU_SFLASH_CNTL__RDMASK                                 0x0000000f
#define APER_PCU_SFLASH_CNTL__WOMASK                                 0x00000000

#define mmAPER_PCU_SFLASH_CNTL                                       0x280C

#define APER_PCU_SFLASH_CNTL__APERSIZE__SIZE                         4
#define APER_PCU_SFLASH_CNTL__APERSIZE__MASK                         0x0000000f
#define APER_PCU_SFLASH_CNTL__APERSIZE__SHIFT                        0



/* REGISTER:  APER_PCU_PFLASH_ADDR */

#define APER_PCU_PFLASH_ADDR__SIZE                                   32
#define APER_PCU_PFLASH_ADDR__BYTELANE                               0
#define APER_PCU_PFLASH_ADDR__WRMASK                                 0xffffffff
#define APER_PCU_PFLASH_ADDR__RDMASK                                 0xffffffff
#define APER_PCU_PFLASH_ADDR__WOMASK                                 0x00000000

#define mmAPER_PCU_PFLASH_ADDR                                       0x2810

#define APER_PCU_PFLASH_ADDR__BASE_ADDRESS__SIZE                     16
#define APER_PCU_PFLASH_ADDR__BASE_ADDRESS__MASK                     0x0000ffff
#define APER_PCU_PFLASH_ADDR__BASE_ADDRESS__SHIFT                    0
#define APER_PCU_PFLASH_ADDR__BASE_OUT__SIZE                         16
#define APER_PCU_PFLASH_ADDR__BASE_OUT__MASK                         0xffff0000
#define APER_PCU_PFLASH_ADDR__BASE_OUT__SHIFT                        16

/* REGISTER:  APER_PCU_PFLASH_CNTL */

#define APER_PCU_PFLASH_CNTL__SIZE                                   32
#define APER_PCU_PFLASH_CNTL__BYTELANE                               0
#define APER_PCU_PFLASH_CNTL__WRMASK                                 0x0000000f
#define APER_PCU_PFLASH_CNTL__RDMASK                                 0x0000000f
#define APER_PCU_PFLASH_CNTL__WOMASK                                 0x00000000

#define mmAPER_PCU_PFLASH_CNTL                                       0x2814

#define APER_PCU_PFLASH_CNTL__APERSIZE__SIZE                         4
#define APER_PCU_PFLASH_CNTL__APERSIZE__MASK                         0x0000000f
#define APER_PCU_PFLASH_CNTL__APERSIZE__SHIFT                        0


/* REGISTER:  APER_CP_PCIC1_ADDR */

#define APER_CP_PCIC1_ADDR__SIZE                                     32
#define APER_CP_PCIC1_ADDR__BYTELANE                                 0
#define APER_CP_PCIC1_ADDR__WRMASK                                   0xffffffff
#define APER_CP_PCIC1_ADDR__RDMASK                                   0xffffffff
#define APER_CP_PCIC1_ADDR__WOMASK                                   0x00000000

#define mmAPER_CP_PCIC1_ADDR                                         0x4000

#define APER_CP_PCIC1_ADDR__BASE_ADDRESS__SIZE                       16
#define APER_CP_PCIC1_ADDR__BASE_ADDRESS__MASK                       0x0000ffff
#define APER_CP_PCIC1_ADDR__BASE_ADDRESS__SHIFT                      0
#define APER_CP_PCIC1_ADDR__BASE_OUT__SIZE                           16
#define APER_CP_PCIC1_ADDR__BASE_OUT__MASK                           0xffff0000
#define APER_CP_PCIC1_ADDR__BASE_OUT__SHIFT                          16



/* REGISTER:  APER_CP_PCIC1_CNTL */

#define APER_CP_PCIC1_CNTL__SIZE                                     32
#define APER_CP_PCIC1_CNTL__BYTELANE                                 0
#define APER_CP_PCIC1_CNTL__WRMASK                                   0x0000730f
#define APER_CP_PCIC1_CNTL__RDMASK                                   0x0000730f
#define APER_CP_PCIC1_CNTL__WOMASK                                   0x00000000

#define mmAPER_CP_PCIC1_CNTL                                         0x4004

#define APER_CP_PCIC1_CNTL__APERSIZE__SIZE                           4
#define APER_CP_PCIC1_CNTL__APERSIZE__MASK                           0x0000000f
#define APER_CP_PCIC1_CNTL__APERSIZE__SHIFT                          0
#define APER_CP_PCIC1_CNTL__SWAP__SIZE                               2
#define APER_CP_PCIC1_CNTL__SWAP__MASK                               0x00000300
#define APER_CP_PCIC1_CNTL__SWAP__SHIFT                              8
#define APER_CP_PCIC1_CNTL__PCI_ATYPE__SIZE                          3
#define APER_CP_PCIC1_CNTL__PCI_ATYPE__MASK                          0x00007000
#define APER_CP_PCIC1_CNTL__PCI_ATYPE__SHIFT                         12



/* REGISTER:  APER_CP_PCIC2_ADDR */

#define APER_CP_PCIC2_ADDR__SIZE                                     32
#define APER_CP_PCIC2_ADDR__BYTELANE                                 0
#define APER_CP_PCIC2_ADDR__WRMASK                                   0xffffffff
#define APER_CP_PCIC2_ADDR__RDMASK                                   0xffffffff
#define APER_CP_PCIC2_ADDR__WOMASK                                   0x00000000

#define mmAPER_CP_PCIC2_ADDR                                         0x4008

#define APER_CP_PCIC2_ADDR__BASE_ADDRESS__SIZE                       16
#define APER_CP_PCIC2_ADDR__BASE_ADDRESS__MASK                       0x0000ffff
#define APER_CP_PCIC2_ADDR__BASE_ADDRESS__SHIFT                      0
#define APER_CP_PCIC2_ADDR__BASE_OUT__SIZE                           16
#define APER_CP_PCIC2_ADDR__BASE_OUT__MASK                           0xffff0000
#define APER_CP_PCIC2_ADDR__BASE_OUT__SHIFT                          16



/* REGISTER:  APER_CP_PCIC2_CNTL */

#define APER_CP_PCIC2_CNTL__SIZE                                     32
#define APER_CP_PCIC2_CNTL__BYTELANE                                 0
#define APER_CP_PCIC2_CNTL__WRMASK                                   0x0000730f
#define APER_CP_PCIC2_CNTL__RDMASK                                   0x0000730f
#define APER_CP_PCIC2_CNTL__WOMASK                                   0x00000000

#define mmAPER_CP_PCIC2_CNTL                                         0x400C

#define APER_CP_PCIC2_CNTL__APERSIZE__SIZE                           4
#define APER_CP_PCIC2_CNTL__APERSIZE__MASK                           0x0000000f
#define APER_CP_PCIC2_CNTL__APERSIZE__SHIFT                          0
#define APER_CP_PCIC2_CNTL__SWAP__SIZE                               2
#define APER_CP_PCIC2_CNTL__SWAP__MASK                               0x00000300
#define APER_CP_PCIC2_CNTL__SWAP__SHIFT                              8
#define APER_CP_PCIC2_CNTL__PCI_ATYPE__SIZE                          3
#define APER_CP_PCIC2_CNTL__PCI_ATYPE__MASK                          0x00007000
#define APER_CP_PCIC2_CNTL__PCI_ATYPE__SHIFT                         12


/* REGISTER:  PCU_INT_CNTL */

#define PCU_INT_CNTL__SIZE                                           32
#define PCU_INT_CNTL__BYTELANE                                       0
#define PCU_INT_CNTL__WRMASK                                         0x007fff3f
#define PCU_INT_CNTL__RDMASK                                         0x007fff3f
#define PCU_INT_CNTL__WOMASK                                         0x00000000

#define mmPCU_INT_CNTL                                               0x0A10

#define PCU_INT_CNTL__DMA_INT_EN__SIZE                               1
#define PCU_INT_CNTL__DMA_INT_EN__MASK                               0x00000001
#define PCU_INT_CNTL__DMA_INT_EN__SHIFT                              0
#define PCU_INT_CNTL__UIRT_EN__SIZE                                  1