xilleonreg_kernel.h

for mips adm5120 uclibc-0.9.19 toolchain

/*
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2002 ATI Technologies, Inc.
 *
 */


/* REGISTER:  MIPS_CNTL */

#define MIPS_CNTL__SIZE                                              32
#define MIPS_CNTL__BYTELANE                                          0
#define MIPS_CNTL__WRMASK                                            0x00317b15
#define MIPS_CNTL__RDMASK                                            0x0011ff15
#define MIPS_CNTL__WOMASK                                            0x00200000

#define mmMIPS_CNTL                                                  0x3810

#define MIPS_CNTL__COLD_RESET__SIZE                                  1
#define MIPS_CNTL__COLD_RESET__MASK                                  0x00000001
#define MIPS_CNTL__COLD_RESET__SHIFT                                 0
#define MIPS_CNTL__NMI_INT_EN__SIZE                                  1
#define MIPS_CNTL__NMI_INT_EN__MASK                                  0x00000004
#define MIPS_CNTL__NMI_INT_EN__SHIFT                                 2
#define MIPS_CNTL__WARM_RESET__SIZE                                  1
#define MIPS_CNTL__WARM_RESET__MASK                                  0x00000010
#define MIPS_CNTL__WARM_RESET__SHIFT                                 4
#define MIPS_CNTL__EJ_PCI_EN__SIZE                                   1
#define MIPS_CNTL__EJ_PCI_EN__MASK                                   0x00000100
#define MIPS_CNTL__EJ_PCI_EN__SHIFT                                  8
#define MIPS_CNTL__EJ_TRST_N__SIZE                                   1
#define MIPS_CNTL__EJ_TRST_N__MASK                                   0x00000200
#define MIPS_CNTL__EJ_TRST_N__SHIFT                                  9
#define MIPS_CNTL__EJ_TDO_TRI__SIZE                                  1
#define MIPS_CNTL__EJ_TDO_TRI__MASK                                  0x00000400
#define MIPS_CNTL__EJ_TDO_TRI__SHIFT                                 10
#define MIPS_CNTL__EJ_DINT__SIZE                                     1
#define MIPS_CNTL__EJ_DINT__MASK                                     0x00000800
#define MIPS_CNTL__EJ_DINT__SHIFT                                    11
#define MIPS_CNTL__EJ_TCLK__SIZE                                     1
#define MIPS_CNTL__EJ_TCLK__MASK                                     0x00001000
#define MIPS_CNTL__EJ_TCLK__SHIFT                                    12
#define MIPS_CNTL__EJ_TMS__SIZE                                      1
#define MIPS_CNTL__EJ_TMS__MASK                                      0x00002000
#define MIPS_CNTL__EJ_TMS__SHIFT                                     13
#define MIPS_CNTL__EJ_TDI__SIZE                                      1
#define MIPS_CNTL__EJ_TDI__MASK                                      0x00004000
#define MIPS_CNTL__EJ_TDI__SHIFT                                     14
#define MIPS_CNTL__EJ_TDO__SIZE                                      1
#define MIPS_CNTL__EJ_TDO__MASK                                      0x00008000
#define MIPS_CNTL__EJ_TDO__SHIFT                                     15
#define MIPS_CNTL__MIPS_PM_CNT_SEL__SIZE                             1
#define MIPS_CNTL__MIPS_PM_CNT_SEL__MASK                             0x00010000
#define MIPS_CNTL__MIPS_PM_CNT_SEL__SHIFT                            16
#define MIPS_CNTL__MIPS_PM_CNT_EN__SIZE                              1
#define MIPS_CNTL__MIPS_PM_CNT_EN__MASK                              0x00100000
#define MIPS_CNTL__MIPS_PM_CNT_EN__SHIFT                             20
#define MIPS_CNTL__MIPS_PM_CNT_CLR__SIZE                             1
#define MIPS_CNTL__MIPS_PM_CNT_CLR__MASK                             0x00200000
#define MIPS_CNTL__MIPS_PM_CNT_CLR__SHIFT                            21




/* REGISTER:  HBIU_VENDOR_ID */

#define HBIU_VENDOR_ID__SIZE                                         16
#define HBIU_VENDOR_ID__BYTELANE                                     0
#define HBIU_VENDOR_ID__WRMASK                                       0x00000000
#define HBIU_VENDOR_ID__RDMASK                                       0x0000ffff
#define HBIU_VENDOR_ID__WOMASK                                       0x00000000

#define pcihbiuHBIU_VENDOR_ID                                        0x0000
#define mmHBIU_VENDOR_ID                                             0x0F00

#define HBIU_VENDOR_ID__VENDOR_ID__SIZE                              16
#define HBIU_VENDOR_ID__VENDOR_ID__MASK                              0x0000ffff
#define HBIU_VENDOR_ID__VENDOR_ID__SHIFT                             0

/* REGISTER:  HBIU_DEVICE_ID */

#define HBIU_DEVICE_ID__SIZE                                         16
#define HBIU_DEVICE_ID__BYTELANE                                     2
#define HBIU_DEVICE_ID__WRMASK                                       0x00000000
#define HBIU_DEVICE_ID__RDMASK                                       0x0000ffff
#define HBIU_DEVICE_ID__WOMASK                                       0x00000000

#define pcihbiuHBIU_DEVICE_ID                                        0x0002
#define mmHBIU_DEVICE_ID                                             0x0F02

#define HBIU_DEVICE_ID__DEVICE_ID__SIZE                              16
#define HBIU_DEVICE_ID__DEVICE_ID__MASK                              0x0000ffff
#define HBIU_DEVICE_ID__DEVICE_ID__SHIFT                             0


/* REGISTER:  GPIO_SEL */

#define GPIO_SEL__SIZE                                               32
#define GPIO_SEL__BYTELANE                                           0
#define GPIO_SEL__WRMASK                                             0x0003ffff
#define GPIO_SEL__RDMASK                                             0x0003ffff
#define GPIO_SEL__WOMASK                                             0x00000000

#define mmGPIO_SEL                                                   0x0880

#define GPIO_SEL__GPIO_SELECTION__SIZE                               18
#define GPIO_SEL__GPIO_SELECTION__MASK                               0x0003ffff
#define GPIO_SEL__GPIO_SELECTION__SHIFT                              0

/* REGISTER:  GPIOA_DATA */

#define GPIOA_DATA__SIZE                                             32
#define GPIOA_DATA__BYTELANE                                         0
#define GPIOA_DATA__WRMASK                                           0x00003fff
#define GPIOA_DATA__RDMASK                                           0x00003fff
#define GPIOA_DATA__WOMASK                                           0x00000000

#define mmGPIOA_DATA                                                 0x0884

#define GPIOA_DATA__GPIO_DATA__SIZE                                  14
#define GPIOA_DATA__GPIO_DATA__MASK                                  0x00003fff
#define GPIOA_DATA__GPIO_DATA__SHIFT                                 0

/* REGISTER:  GPIOA_DIR */

#define GPIOA_DIR__SIZE                                              32
#define GPIOA_DIR__BYTELANE                                          0
#define GPIOA_DIR__WRMASK                                            0x00003fff
#define GPIOA_DIR__RDMASK                                            0x00003fff
#define GPIOA_DIR__WOMASK                                            0x00000000

#define mmGPIOA_DIR                                                  0x0888

#define GPIOA_DIR__GPIO_DIRECTION__SIZE                              14
#define GPIOA_DIR__GPIO_DIRECTION__MASK                              0x00003fff
#define GPIOA_DIR__GPIO_DIRECTION__SHIFT                             0

/* REGISTER:  GPIOA_MASK */

#define GPIOA_MASK__SIZE                                             32
#define GPIOA_MASK__BYTELANE                                         0
#define GPIOA_MASK__WRMASK                                           0x00003fff
#define GPIOA_MASK__RDMASK                                           0x00003fff
#define GPIOA_MASK__WOMASK                                           0x00000000

#define mmGPIOA_MASK                                                 0x088C

#define GPIOA_MASK__GPIO_MASK__SIZE                                  14
#define GPIOA_MASK__GPIO_MASK__MASK                                  0x00003fff
#define GPIOA_MASK__GPIO_MASK__SHIFT                                 0

/* REGISTER:  GPIOB_DATA */

#define GPIOB_DATA__SIZE                                             32
#define GPIOB_DATA__BYTELANE                                         0
#define GPIOB_DATA__WRMASK                                           0x000fffff
#define GPIOB_DATA__RDMASK                                           0x000fffff
#define GPIOB_DATA__WOMASK                                           0x00000000

#define mmGPIOB_DATA                                                 0x0894

#define GPIOB_DATA__GPIO_DATA__SIZE                                  20
#define GPIOB_DATA__GPIO_DATA__MASK                                  0x000fffff
#define GPIOB_DATA__GPIO_DATA__SHIFT                                 0

/* REGISTER:  GPIOB_DIR */

#define GPIOB_DIR__SIZE                                              32
#define GPIOB_DIR__BYTELANE                                          0
#define GPIOB_DIR__WRMASK                                            0x000fffff
#define GPIOB_DIR__RDMASK                                            0x000fffff
#define GPIOB_DIR__WOMASK                                            0x00000000

#define mmGPIOB_DIR                                                  0x0898

#define GPIOB_DIR__GPIO_DIRECTION__SIZE                              20
#define GPIOB_DIR__GPIO_DIRECTION__MASK                              0x000fffff
#define GPIOB_DIR__GPIO_DIRECTION__SHIFT                             0

/* REGISTER:  GPIOB_MASK */

#define GPIOB_MASK__SIZE                                             32
#define GPIOB_MASK__BYTELANE                                         0
#define GPIOB_MASK__WRMASK                                           0x000fffff
#define GPIOB_MASK__RDMASK                                           0x000fffff
#define GPIOB_MASK__WOMASK                                           0x00000000

#define mmGPIOB_MASK                                                 0x089C

#define GPIOB_MASK__GPIO_MASK__SIZE                                  20
#define GPIOB_MASK__GPIO_MASK__MASK                                  0x000fffff
#define GPIOB_MASK__GPIO_MASK__SHIFT                                 0

/* REGISTER:  GPIOA_DATA_FROM_PAD */

#define GPIOA_DATA_FROM_PAD__SIZE                                    32
#define GPIOA_DATA_FROM_PAD__BYTELANE                                0
#define GPIOA_DATA_FROM_PAD__WRMASK                                  0x00000000
#define GPIOA_DATA_FROM_PAD__RDMASK                                  0x00003fff
#define GPIOA_DATA_FROM_PAD__WOMASK                                  0x00000000

#define mmGPIOA_DATA_FROM_PAD                                        0x08A0

#define GPIOA_DATA_FROM_PAD__GPIO_DATA_A__SIZE                       14
#define GPIOA_DATA_FROM_PAD__GPIO_DATA_A__MASK                       0x00003fff
#define GPIOA_DATA_FROM_PAD__GPIO_DATA_A__SHIFT                      0

/* REGISTER:  GPIOB_DATA_FROM_PAD */